quantum computer engineers

Abstract: Scalable cryogenic systems require memory that combines nonvolatile storage, selective access, low thermal disturbance, and compatibility with superconducting electronics. We present a cryogenic memory architecture that integrates a voltage-controlled Josephson junction field-effect transistor (JJFET) selector with a ferroelectric superconducting quantum interference device (FeSQUID) storage element, hereafter termed JFS-CryoMem. The JJFET provides gate-controlled cell selection, whereas the FeSQUID stores information in stable remanent-polarization states. JFS-CryoMem features separate read and write path mechanisms that support nondestructive readout and independent optimization of programming and sensing conditions. The architecture is evaluated using experimentally calibrated compact models that reproduce the measured electrical characteristics of both constituent devices. We demonstrate selective programming using a half-bias scheme, nonvolatile state retention, and distinguishable readout in a $4 \times 4$ array while accounting for the selected cell and all unselected parallel branches. We then extend the analysis to arrays up to $16 \times 16$ and examine how array scaling alters current distribution, column-equivalent resistance, readout separation, required bitline current, and read energy. The results reveal the principal sensing and energy tradeoffs associated with larger arrays and identify the operating conditions required to preserve read distinguishability as the array grows. JFS-CryoMem provides a device-to-array framework for cryogenic memory in quantum, high-performance, and space-oriented computing systems.

Abstract: Scalable memory systems that satisfy the temperature, speed, and energy requirements of cryogenic environments are essential for the development of large-scale quantum computers. They may also benefit high-performance computing and space applications. However, existing cryogenic memory technologies often suffer from limited scalability, low operating speed, and/or high power consumption, restricting the scalability of target applications. Ferroelectric Josephson field-effect transistors (Fe-JoFETs), which combine ferroelectric polarization with the superconducting properties of Josephson junctions, offer a promising solution. The ferroelectric layer enables nonvolatile storage capability, while the Josephson junction supports high-speed, energy-efficient operations. In this work, we leverage Fe-JoFETs to develop a highly scalable, ultra-low-power, nonvolatile cryogenic memory array that does not need additional selector devices for random access. Moreover, the superconducting component of Fe-JoFET provides a binary decision during read, eliminating the need for sensing peripheral circuitry. We first develop a physics-based Verilog-A compact model for Fe-JoFETs and use it to verify the functionality of the proposed memory array. By eliminating both selector and sensing circuitry, the proposed memory architecture offers higher scalability than existing technologies. The ultra-low-power operation of this memory also makes it compatible with strict power budgets of cryogenic applications.

Abstract: We prove quantum soundness of the total-degree diagonal line-vs-point test using the individual-degree soundness theorem of Ji, Natarajan, Vidick, Wright, and Yuen. A random change of coordinates yields projective polynomial decoders of total degree at most $md$. The uniform-line slice of the test bounds the weight of outcomes of degree greater than $d$, which are removed by a common relabeling. This reduction does not yield a dimension-independent soundness bound: the $\operatorname{poly}(m)$ dependence of the individual-degree theorem persists, as discussed in Section 1.2 of arXiv:2009.12982.