Cryogenic memory achieves low energy writes with voltage control devices
JFS-CryoMem: A Cryogenic Memory with Voltage-Controlled Superconducting Devices and Femtojoule-Scale Write/Read Energies
Emerging Technologies
Summary
Memory systems that work at very low temperatures need to be reliable, fast, and use little energy. The authors developed a special memory that uses superconducting devices controlled by voltage to store and read information without losing it when powered off. This memory design allows reading data without erasing it and can be scaled up to larger sizes while keeping energy use very low. Their tests showed how the memory works well in small arrays and predicted how it behaves when made bigger.
What this means in practice
- •For quantum computer engineers: Integrate low-energy, nonvolatile memory compatible with superconducting quantum circuits for scalable quantum system control and data storage.
- •For high performance computing teams: Implement energy-efficient cryogenic memory modules to reduce power consumption and thermal loads in superconducting data center hardware.
Authors
Md Rahatul Islam Udoy, Md Mazharul Islam, Juan P. Mendez, Denis Mamaluy, Aaron J. Muhowski, Samuel Hawkins, William M. Martinez, Courtney Sovinec, Wei Pan, Ahmedullah Aziz
Abstract
Scalable cryogenic systems require memory that combines nonvolatile storage, selective access, low thermal disturbance, and compatibility with superconducting electronics. We present a cryogenic memory architecture that integrates a voltage-controlled Josephson junction field-effect transistor (JJFET) selector with a ferroelectric superconducting quantum interference device (FeSQUID) storage element, hereafter termed JFS-CryoMem. The JJFET provides gate-controlled cell selection, whereas the FeSQUID stores information in stable remanent-polarization states. JFS-CryoMem features separate read and write path mechanisms that support nondestructive readout and independent optimization of programming and sensing conditions. The architecture is evaluated using experimentally calibrated compact models that reproduce the measured electrical characteristics of both constituent devices. We demonstrate selective programming using a half-bias scheme, nonvolatile state retention, and distinguishable readout in a $4 \times 4$ array while accounting for the selected cell and all unselected parallel branches. We then extend the analysis to arrays up to $16 \times 16$ and examine how array scaling alters current distribution, column-equivalent resistance, readout separation, required bitline current, and read energy. The results reveal the principal sensing and energy tradeoffs associated with larger arrays and identify the operating conditions required to preserve read distinguishability as the array grows. JFS-CryoMem provides a device-to-array framework for cryogenic memory in quantum, high-performance, and space-oriented computing systems.