Papers for

chip designers

Papers whose findings have a practical use for this group, as judged from the abstract. Open a paper to read what it means in practice.

Chip area and power cut with clever stacked transistor design

System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability

Abstract: Complementary FETs (CFETs) extend nanosheet FET (NSFET) scaling by vertically stacking n- and p-type gate-all-around (GAA) devices, thereby shrinking standard-cell area. The performance gain, however, cannot be assessed from device metrics alone, as CFET layouts also introduce larger cell-level parasitic resistance and capacitance (RC). In this work, we present a physics-based thermal- and aging-aware system-technology co-evaluation (STCO) flow to assess parasitic RCs in A7 CFET and A10 NSFET technology nodes. Our flow links calibrated device models, optimized standard-cell generation, automated GDS-to-TCAD conversion enabling accurate 3D parasitic RC extraction, full RTL-to-GDS implementation for an AI accelerator, multiphysics thermal analysis, and physics-based bias temperature instability (BTI) aging evaluation. Using the same device model for both technologies, we can isolate the impact of parasitic RCs and design at different levels of the design flow. The results of the AI accelerator design demonstrate that the A7 CFET reduces the chip area by 24.7% and the total wire length by 12%, improving the area efficiency TOPS/mm^2 by 74% relative to the baseline of the A10 NSFET. Under iso-frequency operation, results reveal that CFET voltage scaling reduces power by 68% and lowers power density from 148 W/cm^2 to 55 W/cm^2, which reduces the chip's temperature from 125 degrees C down to merely 62 degrees C. The resulting reduction in stress temperature suppresses 10-year BTI-induced degradation by 39%, reducing the required aging timing guardband by 53%.

Mon 14 SeptEmerging Technologies
The gist
Shrinking computer chips while keeping them fast and reliable is tricky because new designs can cause unwanted slowdowns and wear over time. The authors studied two types of tiny transistor technologies—one stacks parts vertically to save space, the other uses a different layout. They developed a detailed method to see how these designs affect chip speed, heat, and long-term wear. Their tests show the stacked design saves a lot of space, uses less power, runs cooler, and ages more slowly than the other design.
Open → 2609.15326v1

NeuroFlex boosts deep learning speed and energy use by mixing modes

NeuroFlex: Lossless Element-Level ANN-SNN Co-Execution for Efficient Sparse Inference

Abstract: Sparse DNN accelerators specialize in ANN or SNN execution, leaving energy or latency on the table when workload characteristics vary within a layer. Hybrid accelerator designs that switch modes at layer or tile granularity suffer from low PE utilization since one core type idles whenever the other is active. NeuroFlex is the first accelerator to assign every output element independently to ANN or SNN execution mode with zero accuracy loss. We extend integer-exact ANN-SNN equivalence from layers to individual output elements, thereby enabling mode switching with no conversion error. An offline cost-guided scheduler scores each element by its marginal energy-delay trade-off and packs work across PEs, achieving 97-99% PE utilization compared to 40-45% for layer-wise hybrids. NeuroFlex reduces EDP by 57-67% over a strong ANN-only baseline and delivers up to 2.5x speedup over a dual-sparse SNN-only baseline. Our cost-guided scheduler improves throughput by 16-19% over random element assignment across vision, language, and transformer workloads.

Sat 12 SeptHardware ArchitectureMachine Learning
The gist
Often, specialized chips run only one type of deep learning model, either artificial neural networks (ANNs) or spiking neural networks (SNNs), leading to inefficiencies when both are useful. The authors introduce NeuroFlex, a chip that can switch at the level of individual outputs between ANN and SNN modes without losing accuracy. This fine-grained switching improves how busy the chip's processing units stay, cutting delays and energy use significantly. Their smart scheduler decides which mode to use for each output, making inference faster and more energy efficient across various tasks.
Open → 2609.14092v1

Two-transistor one-rram chip enables more reliable in-memory computing

OTTER - Two Transistor - One RRAM Architecture for Reliable In-Memory-Computing in 28 nm CMOS Technology

Abstract: This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.

Tue 8 SeptEmerging Technologies
The gist
Computers often struggle with efficiently doing calculations where data is stored, known as in-memory computing. The authors present OTTER, a tiny computer chip design using a special memory cell with two types of transistors along with a memristor to make these calculations more reliable and precise. They carefully tested and simulated different transistor setups to find the best sizes for each transistor to control how the memory cell works. OTTER can change its memory in small steps, allowing for multiple values to be stored and used in calculations. They also built a small array of these cells to demonstrate how this setup can do the important multiply-and-accumulate operations used in many computer tasks.
Open → 2609.08898v1