Chip area and power cut with clever stacked transistor design
System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability
Emerging Technologies
Summary
Shrinking computer chips while keeping them fast and reliable is tricky because new designs can cause unwanted slowdowns and wear over time. The authors studied two types of tiny transistor technologies—one stacks parts vertically to save space, the other uses a different layout. They developed a detailed method to see how these designs affect chip speed, heat, and long-term wear. Their tests show the stacked design saves a lot of space, uses less power, runs cooler, and ages more slowly than the other design.
What this means in practice
- •For chip designers: Optimize AI accelerator chips to reduce area, power, and aging by using stacked CFET technology with detailed parasitic and thermal modeling.
- •For hardware reliability engineers: Improve long-term chip reliability assessments by integrating temperature-aware aging models with parasitic effect analysis for new transistor designs.
Authors
Mahdi Benkhelifa, Leon Mayr, Hadi Nour Eddine, Andrea Padovani, Luca Larcher, Hussam Amrouch
Abstract
Complementary FETs (CFETs) extend nanosheet FET (NSFET) scaling by vertically stacking n- and p-type gate-all-around (GAA) devices, thereby shrinking standard-cell area. The performance gain, however, cannot be assessed from device metrics alone, as CFET layouts also introduce larger cell-level parasitic resistance and capacitance (RC). In this work, we present a physics-based thermal- and aging-aware system-technology co-evaluation (STCO) flow to assess parasitic RCs in A7 CFET and A10 NSFET technology nodes. Our flow links calibrated device models, optimized standard-cell generation, automated GDS-to-TCAD conversion enabling accurate 3D parasitic RC extraction, full RTL-to-GDS implementation for an AI accelerator, multiphysics thermal analysis, and physics-based bias temperature instability (BTI) aging evaluation. Using the same device model for both technologies, we can isolate the impact of parasitic RCs and design at different levels of the design flow. The results of the AI accelerator design demonstrate that the A7 CFET reduces the chip area by 24.7% and the total wire length by 12%, improving the area efficiency TOPS/mm^2 by 74% relative to the baseline of the A10 NSFET. Under iso-frequency operation, results reveal that CFET voltage scaling reduces power by 68% and lowers power density from 148 W/cm^2 to 55 W/cm^2, which reduces the chip's temperature from 125 degrees C down to merely 62 degrees C. The resulting reduction in stress temperature suppresses 10-year BTI-induced degradation by 39%, reducing the required aging timing guardband by 53%.