Summary
Computers often struggle with efficiently doing calculations where data is stored, known as in-memory computing. The authors present OTTER, a tiny computer chip design using a special memory cell with two types of transistors along with a memristor to make these calculations more reliable and precise. They carefully tested and simulated different transistor setups to find the best sizes for each transistor to control how the memory cell works. OTTER can change its memory in small steps, allowing for multiple values to be stored and used in calculations. They also built a small array of these cells to demonstrate how this setup can do the important multiply-and-accumulate operations used in many computer tasks.
What this means in practice
- •For hardware engineers: Develop embedded computing chips that integrate reliable analog memory cells for fast multiply-and-accumulate operations on 28 nm technology nodes.
- •For chip designers: Design next-generation memory arrays with improved transistor configurations to enhance RRAM cell reliability and multilevel analog storage.
Authors
Yang Chen, Daniele Storelli, Xinyi Zhao, Ankit Bende, Paul-Philipp Manea, Oliver Artner, Arun Ashok, Kay Winterberg, Godwin Paul, Siyuan Jia, Christian Roth, Sabitha Kusuma, Michael Schiek, Vikas Rana, Dirk Wouters, Stephan Menzel, Andre Zambanini, Christian Grewing, Stefan Wiefels, Susanne Hoffmann-Eifert, John Paul Strachan, Stefan van Waasen, Regina Dittmann
Abstract
This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.