Two transistors improve memory computing reliability in 28 nm chips
OTTER - Two Transistor - One RRAM Architecture for Reliable In-Memory-Computing in 28 nm CMOS Technology
Emerging Technologies
Summary
Computers store and process information using tiny devices called memory cells, but making these both fast and reliable is hard. The researchers introduced a new memory cell design using two different transistors working together with a special memory device, allowing better control during programming. This helps store multiple levels of information accurately and supports efficient computing inside the memory itself. They tested this design with detailed experiments and simulations and showed how it can be used for tasks like fast math operations within memory chips.
RRAMtransistorin-memory computingTaOxvalence-change memorymultilevel cellcontent-addressable memorymultiply-and-accumulate28 nm CMOS technologycrossbar array
Authors
Yang Chen, Daniele Storelli, Xinyi Zhao, Ankit Bende, Paul-Philipp Manea, Oliver Artner, Arun Ashok, Kay Winterberg, Godwin Paul, Siyuan Jia, Christian Roth, Sabitha Kusuma, Michael Schiek, Vikas Rana, Dirk Wouters, Stephan Menzel, Andre Zambanini, Christian Grewing, Stefan Wiefels, Susanne Hoffmann-Eifert, John Paul Strachan, Stefan van Waasen, Regina Dittmann
Abstract
This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.