Fpga speeds up encrypted data processing for safer ai tasks
End-to-End NTT on FPGA for FHE Acceleration
Cryptography and SecurityHardware Architecture
Summary
Working with encrypted data keeps information private but can be very slow, especially for tasks like AI. The authors focus on speeding up a math step called the number theoretic transform (NTT), which helps with processing encrypted information more quickly. They built a special hardware design on an FPGA chip that handles this math much faster than regular CPUs. This makes private AI computations, like neural network inference on encrypted data, run almost twice as fast without compromising security.
What this means in practice
- •For fpga designers: Implement accelerated end-to-end NTT kernels to improve throughput of homomorphic encryption operations on multi-die FPGAs.
- •For privacy focused ai developers: Accelerate encrypted neural network inference by integrating fast NTT acceleration into homomorphic encryption workflows.
Authors
Mohamed Allam, Thomas Spendlhofer, Hugo Sanz-González, Antonio J. Peña
Abstract
Fully homomorphic encryption (FHE) enables privacy-preserving computation on encrypted data without decryption. Despite its strong security guarantees, FHE incurs substantial computational and memory overhead. In FHE-based deep learning inference, on average 63% of the CPU time is spent on the number theoretic transform (NTT) and its inverse (INTT), which reduce the complexity of polynomial multiplication from $O(N^2)$ to $O(N \log N)$. Prior FPGA works follow two approaches: accelerating entire FHE schemes, which yields significant speedups but ties them to specific parameters and algorithms, or accelerating only the NTT, which applies across schemes, algorithms, and libraries. Most FPGA NTT designs require interconnects that grow with parallelism and utilize significant resources, which complicates routing on multi-die FPGAs. Additionally, to the best of our knowledge, end-to-end NTT acceleration within an FHE context has so far been left unexplored. We design a fully unrolled, delay-commutator streaming NTT/INTT kernel, and floorplan it across the three dies of an AMD Alveo V80. At 400 MHz, the kernel transforms a polynomial of $2^{16}$ coefficients every 5.12 $μ$s, the highest throughput among FPGA designs at this size. Offloaded end to end, it is up to 22x faster than the CPU per transform. We integrate the kernel into the Lattigo FHE library and evaluate it end to end. With 128-bit secure parameters, it accelerates core FHE operations, such as key switching and bootstrapping, by 1.8-2.2x, and neural network inference by 1.8-2.1x.