Papers for
fpga designers
Papers whose findings have a practical use for this group, as judged from the abstract. Open a paper to read what it means in practice.
Fpga speeds up encrypted data processing for safer ai tasks
End-to-End NTT on FPGA for FHE Acceleration
Abstract: Fully homomorphic encryption (FHE) enables privacy-preserving computation on encrypted data without decryption. Despite its strong security guarantees, FHE incurs substantial computational and memory overhead. In FHE-based deep learning inference, on average 63% of the CPU time is spent on the number theoretic transform (NTT) and its inverse (INTT), which reduce the complexity of polynomial multiplication from $O(N^2)$ to $O(N \log N)$. Prior FPGA works follow two approaches: accelerating entire FHE schemes, which yields significant speedups but ties them to specific parameters and algorithms, or accelerating only the NTT, which applies across schemes, algorithms, and libraries. Most FPGA NTT designs require interconnects that grow with parallelism and utilize significant resources, which complicates routing on multi-die FPGAs. Additionally, to the best of our knowledge, end-to-end NTT acceleration within an FHE context has so far been left unexplored. We design a fully unrolled, delay-commutator streaming NTT/INTT kernel, and floorplan it across the three dies of an AMD Alveo V80. At 400 MHz, the kernel transforms a polynomial of $2^{16}$ coefficients every 5.12 $μ$s, the highest throughput among FPGA designs at this size. Offloaded end to end, it is up to 22x faster than the CPU per transform. We integrate the kernel into the Lattigo FHE library and evaluate it end to end. With 128-bit secure parameters, it accelerates core FHE operations, such as key switching and bootstrapping, by 1.8-2.2x, and neural network inference by 1.8-2.1x.
FPGA processor timing tweaks reduce multiplication stalls significantly
Memory Admission and Result-Retention Sizing in an RV32IMC FPGA Soft Processor
Abstract: In FPGA soft processors with shared backing block RAM, memory admission can stall a multiplication after its product has been prepared. We study how admission timing changes result retention in PaceRV, our board-tested five-stage RV32IMC core, using fixed binaries and matched dynamic instructions. Offering data requests one edge earlier reduces geometric-mean Embench cycles by 18.2% and retention opportunities from 375,063 to 4,373. Admission and retention cycle gains are conditional and non-additive. Under slower reads, a 99% capture target selects an 18-edge validity window with registered requests and 28 edges with early requests, although no multiplication matched within both measurement intervals waits longer. A predeclared sizing rule predicts opportunity recovery exactly in all finite tests, including kernels excluded from model development. Independent timing analysis closely estimates execution-cycle savings. The results support choosing admission first, then deciding whether to extend validity and sizing it against an explicit capture or missed-opportunity objective.