Speech enhancer cuts FPGA processing time and energy by almost half
Realizing Low-Precision Storage and Sparse Execution in a Folded FPGA Speech Enhancer
Hardware ArchitectureMachine Learning
Summary
Making speech clearer with machines usually uses a lot of computer power and memory. The authors studied a special type of chip called an FPGA to see how to save energy and speed up this process by using fewer bits and skipping some calculations. Their approach cuts the time and energy needed by nearly half while keeping or improving speech quality. They tested their method on a real device, proving it works well.
What this means in practice
- •For embedded system engineers: Design low-power FPGA speech enhancement modules that run faster by removing unnecessary operations and reducing weight precision.
- •For audio device manufacturers: Build portable speech-enhancing devices with longer battery life and real-time processing by applying the sparse and low-precision FPGA accelerator methods.$Commercial implications: Enables compact, energy-efficient speech enhancement hardware appealing to consumer electronics markets.
Authors
Clément Laroche
Abstract
Hardware-aware training often optimizes FPGA resources, latency, or bit operations, but folding changes what compression saves: shared arithmetic decouples precision, weight storage, and scheduled work. We derive training objectives from the measured costs of a folded streaming speech-enhancement accelerator. Mixed-precision weights reduce on-chip storage; structured channel sparsity removes entire operations from the engine schedule. We deploy a bit-exact implementation on the Kria KV260. The best sparse model eliminates 47.3% of convolution MACs, cutting frame time by 45% (1.86 to 1.03 ms) and dynamic energy by 60% (83 to 33 $μ$J/frame) against a storage-priced model measured in the same session, with higher speech quality. Relative to the most efficient dense build measured separately, frame time falls by 42% and energy by 48%. Reducing weight width from 8 to 6 bits lowers dynamic power by 27% but changes frame time by less than 5%. Plain channel group-lasso removes more work than cycle-cost-weighted lasso. Thus, folded-accelerator training should price storage and removable work separately, rather than rely on a single bit-operation metric.