ChroNoC reduces energy and improves timing in neuromorphic chip networks
ChroNoC: A Tableless TDM Circuit-Switched NoC With Delay-Aware Deployment for Time-Sensitive Neuromorphic Computing
Hardware ArchitectureNeural and Evolutionary Computing
Summary
Neuromorphic chips need their parts to talk to each other very precisely and quickly. The authors introduce ChroNoC, a new type of network inside these chips that uses a clever way to send messages without needing big tables. They also created a method called DARSA that carefully plans when messages are sent to reduce crowding and energy use. As a result, their system saves a lot of power and speeds up communication compared to existing methods, while still keeping the timing accurate.
What this means in practice
- •For chip designers: Design energy-efficient on-chip networks for timing-critical neuromorphic processors using ChroNoC’s tableless routing and DARSA scheduling.
- •For hardware engineers: Implement delay-aware communication schedules to reduce network congestion and memory needs in neuromorphic hardware.
Authors
Mohammad Rasoul Roshanshah, Mehdi Modarressi, Saeed Safari
Abstract
Time-sensitive neuromorphic architectures require predictable interconnects to preserve precise event timing. Statically scheduled time-division-multiplexed (TDM) circuit-switched networks-on-chip (NoCs) provide deterministic latency at the cost of linear configuration-memory scaling with schedule depth. Furthermore, jointly optimizing task placement, routing, and scheduling creates an intractable combinatorial search space. Existing deployment frameworks also ignore algorithmic axonal delays by forcing immediate spike injections that increase network contention. This paper proposes a hardware-software co-design to address these challenges. ChroNoC is a tableless TDM NoC that embeds precomputed full-grid broadcast trees into combinational logic as a fixed routing substrate. This fixed substrate reduces deployment to a spatial search via Delay-Aware Reservations and Spatial Annealing (DARSA). DARSA converts axonal delays into periodic scheduling slack to stagger network injections and reduce communication overhead. In a 130nm CMOS process, ChroNoC reduces per-hop energy consumption by more than 75% relative to the evaluated circuit- and packet-switched baselines. On UCI-HAR and N-MNIST workloads, DARSA reduces per-timestep communication cycles by approximately 60% and 45%, respectively, compared with immediate transmission, while also reducing provisioned communication memory. These results demonstrate how combining lightweight TDM switch design with delay-aware deployment improves both hardware efficiency and system-level communication performance while preserving neural event timing.