Smaller and faster mac units improve tiny int8 systolic arrays
MAC units for a 2x2 int8 systolic array on Tiny Tapeout
Hardware Architecture
Summary
This paper looks at improving tiny computer chips that multiply and add numbers in a special way. The authors tested two new designs for these chips to make them either smaller or faster. One design reduces the chip size by a small percentage, while the other speeds up calculations by avoiding long addition delays. They checked their designs very carefully to make sure they work correctly.
What this means in practice
- •For embedded hardware designers: Build smaller or faster int8 systolic array accelerators on resource-limited processes like GF180 using improved MAC unit designs.
- •For edge ai developers: Optimize AI inference chips by integrating efficient MAC units that balance size and speed for low-power edge devices.
Authors
Danila Gorodecky
Abstract
We take the multiply-accumulate (MAC) unit of an open-source 2$\times$2 int8 systolic array taped out on Tiny Tapeout (GF180 process) and propose two replacements. The first one, \emph{hybrid}, uses a different arithmetic structure for each row of the array. It reduces the logic area of one MAC unit by 4--6\% and of the whole chip by 0.7--3.2\% after place and route. The second one, \emph{fused\_eq}, never builds the long carry chain of the accumulation. It shortens the critical path by 20\% for one MAC unit and by 14\% for the whole chip. All numbers come from the standard Tiny Tapeout flow (LibreLane) run in GitHub Actions. Correctness is checked by exhaustive simulation of all $2^{24}$ inputs, a formal equivalence proof, and the original test bench.