embedded hardware designers

Abstract: We take the multiply-accumulate (MAC) unit of an open-source 2$\times$2 int8 systolic array taped out on Tiny Tapeout (GF180 process) and propose two replacements. The first one, \emph{hybrid}, uses a different arithmetic structure for each row of the array. It reduces the logic area of one MAC unit by 4--6\% and of the whole chip by 0.7--3.2\% after place and route. The second one, \emph{fused\_eq}, never builds the long carry chain of the accumulation. It shortens the critical path by 20\% for one MAC unit and by 14\% for the whole chip. All numbers come from the standard Tiny Tapeout flow (LibreLane) run in GitHub Actions. Correctness is checked by exhaustive simulation of all $2^{24}$ inputs, a formal equivalence proof, and the original test bench.

Abstract: In this work we look to neuromorphic computing to solve the power consumption problem that audio denoising neural networks face on edge devices like smartphones, wireless headphones and hearing aids. Spiking neural networks (SNNs) have the potential to solve this problem due to their high activation sparsity and low complexity, however many SOTA SNNs require hardware that supports a mixture of operations to be able to fully perform inference. To solve this problem, we convert SOTA audio denoising neural network Spiking-FullSubNet to a hardware friendly version showing that via QAT and activation function simplification we can achieve $\approx28\times$ improvement in power consumption to 52.9nJ per 32ms audio frame when calculated for custom digital hardware in a 45nm process node. We then propose a digital circuit which by means of a sparsity-aware flexible PE array can perform inference of the heterogeneous compute load of Spiking-FullSubNet, and validate this circuit on a PYNQ-Z1 FPGA achieving a real-time factor of 0.727 at 100MHz.