Graph neural networks explore reinforcement learning setups for chip placement refinement
Design Space Exploration of Reinforcement Learning Configurations for Post-Legalization Placement
Artificial Intelligence
Summary
Placing components efficiently on computer chips is a complex problem that affects performance. The authors studied how well a combination of graph neural networks and reinforcement learning can improve chip layout after an initial placement step. They tested many different versions of this approach on standard benchmarks to see what works best. Their analysis shows what settings help or hinder this method and offers guidance to design better reinforcement learning models for this task.
What this means in practice
- •For chip design engineers: Refine chip component placements after legalization using optimized reinforcement learning configurations tested on benchmarks.
- •For machine learning platform builders: Use the classification approach to select reinforcement learning model designs tailored for structured spatial optimization tasks.
Authors
Foteini Oikonomou, Maria Pantazi-Kypraiou, George Goudroumanis, Pavlos Stoikos, Athanasios Tziouvaras, Christos Anagnostopoulos, Georgios Karakonstantis, George Floros
Abstract
Graph Neural Networks (GNNs) and Reinforcement Learning (RL) have recently been explored for VLSI placement optimization, but their effectiveness for post-legalization placement refinement remains unclear. This paper presents a systematic design space exploration of a GNN-Proximal Policy Optimization (GNN-PPO) framework across three ISPD2015 benchmarks. We evaluate 18 configurations covering reward functions, GNN architectures, action spaces, candidate-set sizes, and training strategies. We analyse the results we obtain to identify pitfalls and to assess the prospects and opportunities of the RL methods for post-legalization placement. On top of that we propose a design classification approach to guide the design decisions of RL models.