Low power spike neural network chip boosts speed and cuts energy
STISA: A 0.16 GOPS/W/PE Single-Shot Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design
Hardware Architecture
Summary
Spiking neural networks (SNNs) are a type of AI that mimics how neurons work and use less energy, but they can be slow and inefficient on hardware. The authors created a new system called STISA that cleverly reduces repeated calculations and speeds up processing by designing both the algorithms and the hardware together. Their approach cuts the number of operations needed and saves power while keeping accuracy high on popular image recognition tasks. The result is a faster, more energy-efficient chip for real-time AI tasks using spike-based neural networks.
What this means in practice
- •For embedded systems engineers: Develop low-latency, energy-efficient AI processors for edge devices with constrained hardware resources using spiking neural networks.
- •For robotics hardware developers: Implement real-time, power-saving spiking neural network accelerators for autonomous robots requiring fast sensory data processing.
Authors
Kainan Wang, Chengyi Yang, Lei Liu, Chengting Yu, Yee Sin Ang, Bo Wang, Aili Wang
Abstract
Spiking neural networks (SNNs) offer great potential for low-power intelligent computing owing to their event-driven nature, yet their deployment is limited by high inference latency and inefficient hardware utilization caused by temporal dependencies. Existing accelerators struggle to balance timesteps, accuracy, and energy efficiency, while hardware-oriented timestep compression remains underexplored. To address these challenges, this work presents STISA, a unified algorithm-hardware co-design framework featuring: (i) a Temporal Splitter Compression (TSC) technique with a Temporal Split Structure (TSS) to reduce temporal redundancy while preserving network dynamics; (ii) a hardware-efficient spatiotemporal parallelism scheme, which co-optimizes dataflow and architecture through a Temporal-Prioritized Output-Stationary (TPOS) mapping and a flexible Block-Mux Streaming (BMS) architecture; and (iii) a joint TSC-TPOS-BMS co-optimization framework featuring a bandwidth-aware resource allocation strategy to achieve balanced accuracy, latency, and energy efficiency across diverse network architectures. On the algorithmic side, TSC reduces synaptic operations by 24.44%-51.71% while achieving competitive accuracies of 96.38%, 81.10%, 68.51%, and 82.40% on CIFAR-10, CIFAR-100, ImageNet, and DVS-CIFAR10, respectively. On the hardware side, FPGA prototypes deliver up to 7.99 speedup, 30.4% power reduction, and 30.1% LUT reduction. Compared with state-of-the-art SNN accelerators, STISA achieves 0.16 GOPS/W/PE, demonstrating its scalability and superior energy efficiency for real-time SNN inference under constrained hardware resources.