TALU chip speeds up RISC-V vector processing with tiled ALU grid
TALU: A Reconfigurable Tiled-ALU Grid for RISC-V
Hardware Architecture
Summary
Standard RISC-V vector processors handle many data points at once but slow down when tasks need many steps or combinations of results. The authors created TALU, a processor with a grid of small arithmetic units working together in a special way to handle these tricky tasks faster. This design runs normal code, long chains of calculations, and multi-lane vector programs all on the same hardware. TALU is shown to be much faster and smaller than comparable RISC-V vector processors.
What this means in practice
- •For chip designers: Build RISC-V cores that execute complex vector reductions and dependent calculations faster with a compact tiled ALU grid.
- •For embedded systems developers: Use TALU-based cores to accelerate computational kernels involving reductions and chained vector expressions in low-area devices.
Authors
Ali Emre Oztas, Can Erim Karsal, Mahir Demir, Mikel Luján
Abstract
Lane-based RISC-V vector processors exploit data parallelism well but pay a recurring cost for two common patterns: reductions, which require a separate tree pass, and deep dependent expression chains, which cannot be fused and are issued as serial vector instructions. We present TALU, a 5-stage RISC-V core whose execute stage is an NxN grid of registered ALU tiles instead of a single ALU. The grid is a reconfigurable, feed-forward spatial fabric: tiles route operands only from non-backward neighbours, and added diagonal forwarding lets a reduction collapse spatially. A minimal custom extension configures the per-tile operation, routing, and per-tile constants, and streams operands through the array. On a single fabric, TALU runs ordinary scalar code, single deep-path expressions, and multi-lane vector kernels. On the benchmark suite of the RISC-V2 vector processor, TALU is 1.8-5.5x faster than RISC-V2 and 4.5-15.5x faster than Vicuna at equal lane count, with a reduction cost (dot÷add) of 1.05x versus 1.96x and 1.26x for the vector cores. A retimed implementation places and routes at 1.03 GHz in 45 nm in 0.30 mm2, half the area of RISC-V2.