Backside clock meshes reduce skew and power in 2 nanometer chips
Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology
Hardware Architecture
Summary
Modern computer chips use clock signals to keep everything working in sync, but these signals can slow down or waste power if not delivered well. The paper explores putting the clock wiring on the back side of very tiny 2 nanometer chips instead of the front, using a new technology that adds metal layers behind the chip. The authors found that this backside approach leads to better timing accuracy, lower power use, and less wiring congestion than traditional front-side clock designs. Their findings come from detailed simulations and optimization methods.
What this means in practice
- •For chip design engineers: Use backside clock meshes to improve clock timing accuracy and reduce power consumption in advanced nanoscale integrated circuits.
- •For semiconductor manufacturing engineers: Incorporate backside power delivery and clock mesh routing techniques to optimize chip layouts without congesting top metal layers.
Authors
Wajid Ali, Muhammad Hadir Khan, Dalton Gaddy, Matthew Guthaus
Abstract
Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power delivery creates a new option: it adds thick, low-resistance metal layers on the back of the wafer, and the power grid does not consume all of them. Flip-flops remain on the frontside; a backside mesh therefore cannot drive them directly, and every connection passes through a through-silicon via. We present the first design-space exploration of backside clock meshes, implemented in OpenROAD on GT2N, a 2 nm nanosheet technology. Four benchmarks (1,938 to 15,311 flip-flops) are explored with multi-objective Bayesian optimization, and every design point is verified by transistor-level SPICE simulation, since the cyclic mesh cannot be evaluated by static timing analysis. Across all four designs, the backside mesh consistently outperforms an identical frontside mesh, with on average 45% lower skew, 25% lower sink slew, 4.5% lower power, and 28% less frontside clock wiring, and its skew spread under 10,000-sample Monte Carlo is a third of the frontside mesh's.