Papers for

semiconductor manufacturing engineers

Papers whose findings have a practical use for this group, as judged from the abstract. Open a paper to read what it means in practice.

Zero-shot wafer defect classification achieves high accuracy with prompt ordering

Zero-Shot Multi-Class Wafer Map Classification with Rule-Ordered Prompts for Large Multimodal Models

Abstract: Wafer-map defect classification often requires labeled data and retraining when production conditions change. We present a training-free six-class framework that combines connected-component highlighting with morphology-, location-, and exclusion-aware prompts for a frozen large multimodal model. On Mixed-WM38 (6,866 maps), multi-region prompting achieves 92.9% macro and 93.8% overall accuracy. On WM811K (9,000 maps), it achieves 79.1% and 81.3%, respectively. Eight alternative rule orders achieve 90.1-91.9% overall accuracy, compared with 93.8% for the selected order.

Mon 26 OctArtificial Intelligence
The gist
Classifying defects on semiconductor wafers usually needs lots of labeled examples and retraining when conditions change. This paper shows a way to classify six types of wafer defect maps without any new training, using a large pretrained AI model with special prompts that focus on features like shape and position. The authors tested their method on two large datasets and found it works very well, even without retraining. They also explored how changing the order of prompt rules affects accuracy.
Open → 2610.35080v1

Wafer defect detection improves with online learning and hyperdimensional computing

Online Open-World Wafer Defect Discovery using Hyperdimensional Computing

Abstract: Conventional wafer defect analysis relies on offline, closed-world classifiers that fail to detect novel, unseen defect signatures emerging during continuous semiconductor manufacturing. To address this, we propose WaferHDC, an online open-world wafer defect discovery framework based on hyperdimensional computing (HDC). The memory-centric architecture of WaferHDC enables rapid anomaly detection and grouping of recurring failures into compact hypervector representations. This allows the memory space to dynamically scale with new defect modes without retraining a static classifier or archiving entire raw wafer history. WaferHDC first models normal spatial distributions, then dynamically groups recurring failures into persistent defect memory without labels or predefined class counts. It outperforms the strongest online baseline by 13.3 p.p. in adjusted Rand index and 10.5 p.p. in normalized mutual information on the industry-standard WM-811K dataset. These results demonstrate the effectiveness of WaferHDC for continuous and open-world wafer defect analysis.

Tue 20 OctMachine Learning
The gist
Detecting new types of defects on semiconductor wafers is important but hard because defects can keep changing over time. The authors propose WaferHDC, a system that learns and remembers normal and abnormal patterns on wafers as they appear, without needing prior labels or fixed categories. This approach uses a special kind of computing called hyperdimensional computing to quickly spot anomalies and group similar defects together. Tests on an industry dataset showed WaferHDC works better than previous online methods at finding and organizing wafer defects continuously.
Open → 2610.28949v1

Backside clock meshes reduce skew and power in 2 nanometer chips

Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology

Abstract: Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power delivery creates a new option: it adds thick, low-resistance metal layers on the back of the wafer, and the power grid does not consume all of them. Flip-flops remain on the frontside; a backside mesh therefore cannot drive them directly, and every connection passes through a through-silicon via. We present the first design-space exploration of backside clock meshes, implemented in OpenROAD on GT2N, a 2 nm nanosheet technology. Four benchmarks (1,938 to 15,311 flip-flops) are explored with multi-objective Bayesian optimization, and every design point is verified by transistor-level SPICE simulation, since the cyclic mesh cannot be evaluated by static timing analysis. Across all four designs, the backside mesh consistently outperforms an identical frontside mesh, with on average 45% lower skew, 25% lower sink slew, 4.5% lower power, and 28% less frontside clock wiring, and its skew spread under 10,000-sample Monte Carlo is a third of the frontside mesh's.

Thu 1 OctHardware Architecture
The gist
Modern computer chips use clock signals to keep everything working in sync, but these signals can slow down or waste power if not delivered well. The paper explores putting the clock wiring on the back side of very tiny 2 nanometer chips instead of the front, using a new technology that adds metal layers behind the chip. The authors found that this backside approach leads to better timing accuracy, lower power use, and less wiring congestion than traditional front-side clock designs. Their findings come from detailed simulations and optimization methods.
Open → 2610.02401v1