Hierarchical reinforcement learning improves chip routing and switch placement
Validity-Preserving Hierarchical RL for Joint Routing and Switch Placement in EDA
Machine Learning
Summary
Designing the internal pathways and placing switches in computer chips is very complicated because there are many rules and constraints to follow. The authors propose a step-by-step learning approach that builds valid designs by adding switches, placing them, and improving routes while always keeping the design workable. Their method uses a smart search guided by AI to find better solutions than traditional methods, and it can learn from past designs to perform well on new chip layouts.
What this means in practice
- •For chip design engineers: Produce higher quality routing and switch placement plans for chip layouts ensuring logical and geometric constraints are met.
- •For electronics manufacturing teams: Use AI-enhanced routing and switch placement to reduce design iteration cycles and improve chip fabrication readiness.
Authors
Dorian Gailhard, Ugo Lecerf, Enzo Tartaglione, Donatello Conte, Jhony H. Giraldo
Abstract
Routing and switch placement are fundamental combinatorial optimization problems in chip design, requiring the joint optimization of routing topology and physical placement under strict structural, geometric and logical constraints. Existing approaches typically rely on carefully engineered heuristics that incorporate strong problem-specific biases to navigate the enormous space of possible designs. In this work, we introduce a hierarchical reinforcement learning framework for joint routing and switch placement at the level of logical communication routes. Starting from a minimal routing graph, our method progressively constructs increasingly expressive solutions through three coupled operations: switch expansion, switch placement, and route refinement. These operations preserve routing validity by construction, restricting exploration to feasible configurations where every communicating initiator-target pair has one assigned loop-free route. We explore the induced solution space using Gumbel Monte Carlo Tree Search, showing that neural-guided search substantially improves solution quality over non-learning optimization methods. Furthermore, pretraining across floorplans provides a strong initialization for fine-tuning on unseen instances.