HARS improves error correction with faster and more reliable decoding
HARS: LDPC Bit-Flipping Decoding With Initial-Syndrome-Conditioned Parameter Mapping and Local-Reliability Weighting
Information Theory
Summary
When digital messages get sent, errors can happen due to noise. The authors developed HARS, a method that better detects and fixes these errors by using information from the first check of the message and local data about reliability. This approach lets the decoding process update many bits at once more efficiently. Tests show it significantly lowers error rates and speeds up decoding compared to older methods. They also demonstrated it working well on a hardware chip, making it practical for real devices.
What this means in practice
- •For communication system engineers: Design decoders for wireless and wired communication systems that achieve lower error rates with fewer decoding steps using HARS.
- •For hardware designers: Implement efficient, parallel decoding hardware on FPGAs that process multiple data frames rapidly with HARS.
Authors
Tung Hsu Wu, Huang-Chang Lee
Abstract
HARS (Hybrid Adaptive Reliability-Aware and Syndrome-Aware) is a bit-flipping decoder that combines local channel reliability with parameter selection from the initial syndrome. A bounded check reliability modifies the parity-check weight, while the initial syndrome weight selects the base weight, reliability coefficient, threshold decay factor, and perturbation amplitude for each frame. Computing these quantities at initialization supports synchronous multi-bit updates with a simple iterative datapath. For rate-one-half PEGReg and WiMAX codes over the binary-input additive white Gaussian noise channel, HARS reduces both bit-error rate (BER) and mean iteration count relative to a calibrated SM-NGDBF baseline. The PEGReg BER at 3.25 dB is approximately one-sixth of the comparison value; the WiMAX BER at 2.75 dB is reduced by 59%. A seven-fractional-bit FPGA implementation shares 132 variable-node lanes among four frame contexts. Precomputed check weights, encoded threshold states, and parallel perturbation generation support one group per clock during sustained decoding. On an XC7A200T at 60 MHz, for preloaded 128-frame batches with a ready receiver, measured coded throughputs are 49.7 Mb/s at 2.50 dB and 361.9 Mb/s at 4.00 dB, including initialization and output transfers.