Analog circuit yield improves faster with new simulation method
Simulation-Efficient Analog Circuit Yield Optimization via Monte Carlo Zeroth-Order Gradient Estimation
Computational Engineering, Finance, and Science
Summary
Optimizing how well circuits perform despite manufacturing differences is usually very slow because each design is tested many times in computer simulations. The authors developed a new way to guess which direction improves circuit yield using fewer simulations by comparing slight design changes under the same test conditions. Their method doesn't require complicated math inside the simulation software or building approximate models. They showed it works well on several example circuits, needing fewer simulations than existing methods to reach high yield.
What this means in practice
- •For analog circuit designers: Speed up designing circuits that meet performance despite manufacturing variability by using fewer costly simulations to improve yield.
- •For semiconductor manufacturing teams: Reduce the number of simulation runs needed to qualify circuit designs under process variation, accelerating time to production.
Authors
Liyan Tan, Yequan Zhao, Ben F. Jamroz, Ari Feldman, Zheng Zhang
Abstract
Yield optimization under process variation is expensive because each candidate design must be evaluated across many Monte Carlo SPICE samples. The resulting finite-sample yield is also piecewise constant in the design parameters, providing little local information for optimization. We introduce zeroth-order Monte Carlo stochastic gradient descent (ZO-MC-SGD), a black-box method that converts continuous specification margins into stochastic descent directions. Each update evaluates opposite design perturbations under shared process samples, allowing a small simulation batch to estimate a local direction without differentiating SPICE or fitting a global surrogate model. A Spearman rank-correlation test checks that the margin-based loss orders designs consistently with empirical yield. We prove that the estimator is unbiased for a Gaussian-smoothed surrogate and derive variance and sample-complexity bounds with no explicit dependence on process dimension. Across five analog circuit benchmarks with up to 30 design variables and 42 process variables, ZO-MC-SGD reaches a mean yield of 0.95 on four circuits within 50--200 simulations and the empirical yield ceiling on the fifth. Relative to the best of five black-box and learning-based baselines, it reduces the required simulation budget by up to a factor of eight.