Power delivery strategies enable bigger advanced 3D chip systems
Toward Multi-kW Power Delivery Methodologies for Advanced 3D Heterogeneous Integration
Hardware Architecture
Summary
Modern computer chips, especially those used for AI, are getting so complex that they need more power than usual to work properly. The authors look at ways to reliably supply large amounts of power to these stacked chip components, which are packed tightly together. They discuss design methods that spread the power in stages throughout the chip system to keep things running smoothly and avoid overheating or failures. This work helps support bigger, faster computer systems by solving tough power supply problems.
What this means in practice
- •For chip designers: Design multistage distributed power systems to reliably supply advanced 3D heterogeneous integrated chips for AI workloads with high power demands.
- •For server hardware engineers: Build high-performance servers that contain large 3D heterogeneous chip stacks by integrating improved power delivery methods for stability and efficiency.
A survey. It maps existing work.
Authors
Peiyi Yue, Hangyu Zhang, Ratul Das, Ramesh Harjani, Sachin S. Sapatnekar
Abstract
The demands of modern applications require the construction of ever more complex integrated systems, with AI applications in particular serving as a significant driver for increased system size, potentially going beyond the trilliontransistor mark. The path to building these systems requires the use of advanced packaging, with heterogeneous integrated 2D and 3D chiplets placed atop a substrate. Such computationally powerful systems require significant power for computation: reliable and robust power delivery is a major challenge in light of high power densities and pin count bottlenecks. This paper overviews approaches to building design methodologies that overcome this problem, through the design of multistage distributed power delivery systems, optimized for performance and reliability, and built to coexist within stringent performance, thermal, and reliability constraints.