Adaptive neurons improve spiking network firing patterns with efficient scaling
DVA-Neurons: Design and Verification of Adaptive LIF Neurons: From Single-Neuron Dynamics to Multi-Neuron Spiking Networks
Artificial IntelligenceHardware Architecture
Summary
Spiking Neural Networks (SNNs) mimic how brain cells send signals to perform actions with very low power. This paper shows how adding adaptation to these artificial brain cells helps them change their activity based on past firing, making their behavior more like natural neurons. The researchers built and tested single adaptive neurons and small networks to verify these improvements. They also developed methods to watch every step inside these neurons as they work, ensuring the designs function correctly. This makes it easier to build larger, more efficient brain-like networks for low-power computing.
What this means in practice
- •For chip designers: Build adaptive neuron models in hardware to achieve more biologically accurate and power-efficient spiking neural processors.
- •For neuromorphic hardware engineers: Design scalable spiking networks with configurable synaptic weights and rigorous per-cycle verification techniques for reliable inference.
Authors
Thanh Pham, Riadul Islam
Abstract
Spiking Neural Networks (SNNs) offer a promising path toward ultra-low-power artificial intelligence inference by emulating the event-driven computation of biological neurons. However, two challenges limit their practical deployment. First, fixed-parameter Leaky Integrate-and-Fire (LIF) neurons lack the adaptation mechanisms observed in biology, where neurons modulate their excitability based on firing history. Second, scaling from single neurons to multi-neuron networks introduces challenges in synaptic weight distribution and inter-neuron spike routing that are absent in isolated designs. This paper addresses both issues through the extension, verification, and physical implementation of adaptive LIF neurons at three architectural scales. This work contributes: a 2nd-order neuron with two-stage synaptic filtering for richer temporal dynamics; a fully-connected 6-neuron spiking network with configurable weights (100 to 5) demonstrating weight-based inter-neuron communication; and a direct verification methodology enabling per-cycle observation of all internal states. All designs were synthesized targeting Selected Area Electron Diffraction (SAED) 14 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology at 1 GHz and verified with Cocotb-based Python testbenches under pulsed current stimuli (amplitude 80, ISI=3). The results show that adaptation effectively modulates firing: 31% suppression in the 2nd-order neuron (25 vs.\ 36 spikes) and 31% reduction in postsynaptic firing in the network (18 vs.\ 26 spikes). Physically, the 2nd-order neuron costs 1.77x more area and 1.52x more power than the 1st-order baseline, while the 6-neuron network demonstrates near-linear scaling (5.7x area, 5.3x power). Seven verification bugs spanning testbench connectivity, fixed-point overflow, and Verilog expression-width semantics are documented.