PlaceReasoner Beta improves macro placement in chip design using reasoning
PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking
Artificial Intelligence
Summary
Designing the layout of computer chips is tricky, especially deciding where to place large parts called macros. Existing methods optimize simple estimates but often miss the bigger picture of design rules and feedback from later steps. The authors propose PlaceReasoner-Beta, which uses a reasoning loop involving visual understanding, rules checking, and feedback to create better layouts. They tested it on various chip designs and found it improves timing and wiring without focusing directly on those metrics.
What this means in practice
- •For chip design teams: Generate more timing-efficient macro placements using a reasoning-driven, multi-agent system integrating visual context and feedback.
- •For eda software developers: Incorporate closed-loop reasoning and verification modules into macro placement tools to improve layout quality beyond traditional proxy optimization.
Authors
Qiufeng Li, Chengxuan Wang, Rongqian Chen, Quan Cheng, Yihui Ren, Chia-Tung Ho, David Z. Pan, Tian Lan, Weidong Cao
Abstract
Automated macro placement remains a fundamental challenge in VLSI physical design. Despite decades of research, existing approaches predominantly optimize hand-crafted proxy objectives, such as estimated wirelength, and typically produce placements through one-shot numerical optimization, limiting their ability to incorporate visual layout context, codified design expertise, and downstream physical-design feedback in a unified loop. We present PlaceReasoner-Beta, a verifier-guided multi-agent framework that reformulates macro placement as a closed-loop reasoning problem rather than black-box optimization. A vision-language model (VLM) planner generates candidate placements from the floorplan image, macro specifications, and connectivity structure; a geometric verifier enforces physical legality and expert placement principles; a physical verifier refines candidates using early implementation feedback; and a post-route optimizer further improves promising layouts using final PPA. To enable reproducible evaluation, we introduce PlaceReasoner-Bench, a fully open end-to-end benchmark built from open RTL designs, EDA tools, and technology libraries. It comprises 8 designs at two aspect ratios, yielding 16 tasks with fixed floorplans and I/O assignments, so methods differ only in macro positions and orientations and are evaluated using routed PPA and DRC rather than pre-route proxies. Across the benchmark, PlaceReasoner-Beta achieves the best timing among DRC-clean methods on all square tasks, reducing post-route TNS by 61.2% at 1:1 and 53.0% at 2:1 relative to the classical baseline field. It also shortens routed wirelength on most designs despite never explicitly optimizing it, demonstrating that reasoning over spatial structure under physical-design feedback can improve end-to-end layout quality beyond proxy-objective optimization.