Power-clock waveforms improve energy efficiency of adiabatic logic in 16 nm chips
Evaluation of Power-Clock Waveforms for Positive Feedback Adiabatic Logic in 16 nm FinFET Technology
Hardware Architecture
Summary
Modern computer chips consume a lot of energy when switching electrical signals on and off. The authors studied a special circuit style called Positive Feedback Adiabatic Logic (PFAL) that can save energy by carefully controlling these switches with specific wave shapes. They found that shaping the power signal like a triangle is more energy-efficient than the often-used trapezoid shape. Using this approach in a 16-nanometer chip design, their circuits used much less energy than traditional designs, especially for certain types of adders. This helps chip designers reduce power consumption in high-speed, tiny transistors.
What this means in practice
- •For chip designers: Design energy-efficient digital circuits in 16 nm FinFET technology using optimized triangular power-clock waveforms for PFAL to reduce power consumption.
- •For hardware engineers: Build low-power high-speed combinational logic like adders and multiplexers using PFAL gates optimized with triangular or sinusoidal power-clock shapes.
Authors
Maciej Szymon Pyrzowski, Franciszek Łukowski, Aida Todri-Sanial
Abstract
Adiabatic logic can recover part of the energy stored on load capacitances through quasi-reversible switching, but its waveform-optimized operation in FinFET technology and at multi-GHz frequencies remains underexplored. This work investigates Positive Feedback Adiabatic Logic (PFAL) in the TSMC 16 nm FinFET process. A functionally complete PFAL gate library is designed, verified, and characterised using energy-delay product optimization over power-clock amplitude, frequency, and waveform shape. The power-clock sweep shows that the minimum-energy waveform approaches a triangular shape rather than a conventional trapezoid. The optimized single-gate PFAL cells achieve up to 3.83x lower energy than equivalent static CMOS gates, while sinusoidal excitation improves energy by up to 1.32x compared with trapezoidal excitation and extends the valid operating range. The library is then used to construct larger combinational circuits, including a 2:1 multiplexer, a 4-bit ripple carry adder, and a 4-bit Brent-Kung carry look-ahead adder. The carry look-ahead adder reaches a gain of up to 5.3x compared with the static CMOS energy estimate for the triangular power-clock.