Optimized high-speed multiply-accumulate unit cuts power and area
High-frequency Multispeculative Multiply-Accumulation Unit for Fused Posit Arithmetic
Hardware Architecture
Summary
Performing complex calculations with special number formats called posits usually needs big hardware parts that use a lot of energy and space. The authors designed a faster and smaller part that does these calculations more efficiently by changing how the work is divided and using a new way to add partial results. This new design runs twice as fast and uses much less energy compared to older versions. It also takes up less space while still delivering precise and reliable results.
What this means in practice
- •For chip designers: Build faster, more energy-efficient posit arithmetic units for AI and scientific computing chips using this multispeculative multiply-accumulate design.
- •For hardware architects: Incorporate balanced pipelines and optimized accumulators to reduce area and power in next-generation arithmetic units supporting posit formats.
Authors
Mario Alonso, Miguel Ángel Sacristán, Guillermo Botella, Alberto A. Del Barrio
Abstract
Posit arithmetic offers a compelling alternative to the IEEE 754 floating-point standard, providing enhanced accuracy. Its fused multiply-accumulate operations avoid intermediate rounding, ensuring exact numerical reproducibility through the quire, a wide fixed-point accumulator spanning the format's full dynamic range to prevent precision loss and overflow during long accumulations. However, integrating such large accumulators incurs significant area and power overheads. This paper presents an optimized, high-frequency Multispeculative PositMAC architecture for 32- and 64-bits Posit. First, the pipeline is restructured to balance the different stages. Second, high-speed multiplication topologies are evaluated, showing that a Booth-4 scheme with Kogge-Stone adders meets a stringent 0.5ns target (2Ghz). Finally, the wide monolithic quire accumulator is replaced with a Multispeculative Adder, diminishing area up to 19.8\% while reducing energy consumption by more than 50\% when compared to the baseline. Compared to other state-of-the-art designs, our proposal achieves the highest operating frequency and reduces cycle time by up to 79.0\% with respect to 64-bit quire-enabled alternatives. This performance is attained without increasing resource overhead, as the design remains strictly smaller in area and achieves lower per-cycle energy consumption than all quire-capable counterparts.