Cgra boosts energy efficiency with single cycle configurable mac units
A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation
Hardware Architecture
Summary
Many small devices need to process data quickly and use very little energy. The authors created a special chip design called a CGRA that can do a multiply-and-add operation in just one step instead of two, making it faster and more efficient. They also added a way to adjust precision dynamically to save even more energy. Their design works well on real hardware and is more energy-efficient than previous similar chips. This can help devices like smart sensors or mobile gadgets run complex tasks without draining their batteries quickly.
What this means in practice
- •For embedded system engineers: Build edge devices that run neural network and signal processing tasks more energy efficiently by using the proposed CGRA with configurable MAC units.
- •For wearable device developers: Create wearables that handle complex real-time data with lower energy use by integrating the single-cycle configured MAC CGRA.
Authors
Yi Sheng Chong, Rakshith Harish, Rajesh Chandrasekhara Panicker, Vishnu P. Nambiar, Anh Tuan Do
Abstract
Edge devices demand for highly efficient yet flexible processing capability to handle dynamic real-time workloads. Coarse grain reconfigurable architecture (CGRA) emerges as a suitable accelerator candidate in edge devices, because they are as flexible as general purpose processors and offer high efficiency close to that of domain specific accelerators. However, a typical CGRA requires two cycles for a multiply-and-accumulate (MAC) operation, and workloads such as neural network inference and signal processing involve many MAC operations, resulting in long CGRA processing time. This work proposes a CGRA that has configurable MAC units in the processing elements (PEs) that can perform an addition (ADD) or multiplication (MUL) or a MAC by using the same multiplier and adder, in a single cycle. The readout precision of MAC result can be adjusted by a truncation block. The proposed CGRA is implemented with 40nm CMOS technology. It attains an energy efficiency of 420.6GOPS/W operating at supply of 0.6V and frequency of 21MHz, which is 1.4 times higher than the state-of-the-art.