Efficient broad learning speeds up harmonic analysis for electric grids
EBL: Efficient Broad Learning for Distributed Adaptive Harmonic Analysis
Hardware ArchitectureMachine Learning
Summary
The increasing use of electric vehicles causes complex electrical distortions in power grids, which can damage equipment over time. The authors developed a fast and accurate way to analyze these distortions using a specialized computer chip called an FPGA. Their method quickly adapts to changing electrical conditions and uses less chip resources than previous approaches. This helps improve monitoring and control of electrical quality in distribution networks.
What this means in practice
- •For power system engineers: Perform real-time harmonic distortion detection in electric vehicle charging stations to protect grid infrastructure efficiently.
- •For embedded systems developers: Implement low-latency harmonic estimators on FPGA platforms for adaptive monitoring in smart electrical devices.
Authors
Changhong Li, Georgios Floros, Biswajit Basu, Shreejith Shanker
Abstract
Renewable energy systems and electrified transport have found widespread adoption in recent years. The integration of these non-linear loads, dominated by electric vehicle (EV) charging, however, has introduced severe harmonic distortion into the power grid, impacting the efficiency and lifetime of substation equipment and switchgear in the distribution network. Rapid and high-precision harmonic analysis has hence become a prerequisite for effective harmonic control at the source of injection. This paper proposes an Efficient Broad Learning (EBL) framework for distributed adaptive harmonic estimation. As a quantised FPGA acceleration framework for BLS-style harmonic estimation, it offers high-accuracy estimation with half-cycle input, reconfigurable flexibility enabled by the FPGA implementation, and ultra-low latency, achieving 17.4 $\times$ faster predictions than the nearest reported FPGA method. For harmonic prediction across multi-scenario charging and discharging nodes, the online transfer learning based on a closed-form solution rather than backpropagation in EBL demonstrates rapid adaptability. By exploiting bespoke quantisation and sparsity, the approach consumes 5.9\% of the LUTs on the Zynq Ultrascale+ ZU7EV FPGA, using $\approx$ 82\% of the LUTs required by the state-of-the-art FPGA-accelerated estimator.