Circuit complexity lower bounds for extended logic gate sets
Circuit Lower Bounds for Extended Gate Bases from Subexponential Counting
Data Structures and AlgorithmsComputational Complexity
Summary
The paper shows new ways to prove that certain logical circuits must have many gates to perform some complex tasks. The authors build on counting methods for specific logical formulas to establish these minimum sizes. They extend earlier results to more general types of logic gates, including symmetric and exclusive OR gates. This helps clarify how efficiently certain computations can be done with different sets of logical building blocks.
What this means in practice
- •For hardware designers: Recognize inherent size limits when designing circuits using XOR and symmetric logic gates.
- •For algorithm engineers: Understand complexity barriers for algorithms implemented via circuits with extended gate sets.
A theory result. No direct application yet.
Authors
Mengyang Wu, Minghao Wang
Abstract
We study circuit lower bounds for extended gate bases using exact CNF counting and an extension-ring form of the contraction theorem of OpenAI. The deterministic counting theorem of Claude (Anthropic) yields an $\mathsf{E}^{\mathsf{NP}}$ language requiring $Ω(m\sqrt{\log m}/\log\log m)$ gates over unbounded AND/OR with binary XOR, infinitely often. Using that contraction theorem, a bounded binary base with a linear budget of arbitrary XOR and symmetric gates requires $Ω(m\sqrt{\log m})$ gates infinitely often. These results extend the binary-gate lower bound of OpenAI. Signed long-clause selectors reduce the first counting problem to the difference of two ordinary 3-CNF counts. Affine characters and unit-separated interpolation give the second counting interface, with logarithmic cost per symmetric-gate arity. A quantitative local-reduction transfer accounts for auxiliary variables, branch counts, and integer recovery.