Cosine-domain CNN boosts energy efficiency on FPGAs for edge AI
Energy-Efficient FPGA Implementation of an End-to-End Cosine-Domain CNN Using High-Level Synthesis
Hardware Architecture
Summary
Convolutional Neural Networks (CNNs) usually need a lot of computing power, which makes them hard to run on small, low-energy devices. The authors designed a version of CNNs that works in the cosine domain, which simplifies calculations and saves energy. They built this design on a specialized chip called an FPGA and tested it on image recognition tasks, showing it uses less power and runs faster than other similar designs. This approach could help bring smarter AI applications to devices with limited battery life and computing resources.
What this means in practice
- •For embedded system developers: Implement energy-efficient CNNs on FPGA hardware for faster and lower-power edge AI inference.
- •For mobile device engineers: Enhance AI applications on battery-powered devices by reducing computational cost with cosine-domain CNNs.
Authors
Sana Fatima, Ab Al-Hadi Ab Rahman, Ibrahim Yousef Alshareef, Farhad Khodadadi, Nuzhat Khan
Abstract
The computational cost of conventional Convolutional Neural Networks (CNNs) limits their deployment in low-power devices for high-speed edge AI applications. This paper presents an end-to-end cosine-domain CNN (CD-CNN) architecture for energy-efficient FPGA inference using high-level synthesis (HLS). The proposed architecture performs intermediate feature extraction using real-valued DCT-domain representations, avoiding complex-valued arithmetic and intermediate inverse transforms between spectral layers. The design is implemented on a Xilinx Kintex UltraScale+ XCKU5P FPGA and evaluated against a fully spectral Fourier-domain CNN (FD-CNN) under consistent network and implementation constraints. Experiments on the MNIST and 94-class ASCII datasets show that the CD-CNN reduces normalized resource utilization and improves inference throughput on both datasets. Its energy efficiency reaches 112.91 frames/J for MNIST and 101.27 frames/J for ASCII, corresponding to improvements of $1.51\times$ and $2.76\times$, respectively, over the fully spectral FD-CNN architecture. Furthermore, compared to the previous GPU-based fully spectral CD-CNN implementation, the proposed end-to-end FPGA implementation improves energy efficiency by $12.96\times$. These results demonstrate the potential of real-valued spectral processing in the DCT domain for energy-efficient edge AI deployment.