Energy efficient cnn inference with selective early exit control
SLICE-CiM: Selective Layer-wise Inference Control Engine with Confidence-Based Early Exit for SRAM based Digital Compute-in-Memory
Hardware ArchitectureNeural and Evolutionary Computing
Summary
Running image recognition AI models inside computer memory chips can save energy, but extra control parts sometimes waste power. The authors designed special circuits that decide when to finish calculations early based on confidence, and manage processing precision carefully. This approach reduces wasted work and power use without changing the memory cell design or needing to retrain AI models. Their system works well for popular AI models like MobileNetV2 on image tasks.
What this means in practice
- •For hardware design engineers: Integrate selective early-exit control logic into SRAM CIM chips to reduce energy waste during CNN inference without hardware cell redesign.
- •For embedded system developers: Deploy energy-efficient CNN inference engines with confidence-based early exit on low-power devices running image classification tasks.
Authors
Pratham Sharma, Mohd Faisal Khan, Santosh Kumar Vishvakarma
Abstract
Digital SRAM compute-in-memory (CIM) macros enable energy-efficient CNN inference by eliminating off-chip weight transfers; however, peripheral control logic introduces three inefficiencies: bit- slice over-activation at reduced precision (L1), unnecessary accumula- tion depth (L2), and idle precision-transition stalls (L3). To address these, we present four synthesizable peripheral blocks: a Flush-Merge Enable (FME) controller, a Confidence-Based Early-Exit (EE) module, a Precision Register with Decoder (PR/PD), and a Bit-Serial Cycle Controller (CC), co-designed to minimize switching activity, wordline overhead, and leakage. Implemented in TSMC 65-nm CMOS at 335 MHz, the peripheral framework occupies 1769.760 μm2 post-synthesis and 1982.131 μm2 post-PnR. Gate-level VCD analysis reports 6.0706 μW leakage and 288.2902 μW (post-synthesis) / 322.8850 μW (post-PnR) dynamic power, totaling 328.9556 μW (0.2402% of system power). The EE module dominates dynamic power (58.2%), while WLG dominates area (58.1%). System evaluation on MobileNetV2 (CIFAR-100) shows efficiency scaling from 31.35 TOPS/W (8b/8b, 1.2 V) to 454.91 TOPS/W (2b/8b, 0.8 V), achieving 13.33x improvement without bitcell modification or retraining. The framework targets CNN workloads exploiting sparsity, with Transformer extension as future work.