State augmented method improves processor design concurrency and efficiency
A State Augmented Approach to Paralle Modeling in High-Level Synthesis
Hardware Architecture
Summary
High-level synthesis (HLS) tools often miss opportunities for parallel operation because they depend entirely on how the design is described. The authors show that using a special way to model processor architecture makes it easier for HLS to schedule tasks more efficiently. Their modeling method lets designers control architectural states and feedback more clearly, enabling better overlap of operations. They tested this on a processor design for an FPGA and achieved faster instruction processing and smaller hardware footprints than standard methods.
What this means in practice
- •For hardware designers: Create FPGA-based processors with improved instruction throughput and configurable area-performance trade-offs by applying explicit architectural state modeling.
- •For embedded systems engineers: Optimize embedded processor designs for speed or area by managing how architectural state and memory accesses are represented in high-level synthesis.
Authors
Nicholas Kovacs, Hao Zheng
Abstract
High-level synthesis (HLS) can schedule only the concurrency made legal by its input description. For feedback-coupled designs, a sequential behavioral model can obscure the architectural state boundaries and hazard resolution needed for efficient overlap. We develop an explicit architectural modeling methodology based on synchronous sequential processes that start in lockstep and synchronize completion before repeating. Persistent state, communication, and feedback control are represented in C++, while HLS schedules and binds operations within that structure. A five-stage RV32I processor illustrates three consequential modeling decisions: which version of a value a consumer reads, when it consumes that value, and how architectural memory actions map to port operations. On a Kintex UltraScale+ FPGA, the CPI-optimized configuration achieves 1.221 cycles per instruction at 220 MHz, compared with 4.000 for an algorithmic HLS baseline and 1.575 at 242 MHz for an Ibex reference. An area-optimized configuration reduces LUTs by 65\% and registers by 47\%, with 9.7\% more benchmark cycles and a 250 MHz achieved clock. These results demonstrate a separation between designer-controlled architecture and tool-controlled scheduling.