Tsetlin machine training cuts inference delay while keeping accuracy
Inference Latency-Aware Tsetlin Machine Training
Machine Learning
Summary
Making smart devices respond quickly is important, but often they have limited computer power. The authors looked at a kind of simple logic-based computer model called the Tsetlin Machine that works well in these small devices. They found a way to adjust how this model is trained so it can make decisions faster without losing much accuracy. Instead of trying lots of settings, they developed a smart search to pick the best training values that speed up the model.
What this means in practice
- •For embedded systems engineers: Optimize Tsetlin Machines for faster decision-making in low-power edge devices by adjusting training parameters to reduce inference delay.
- •For mobile app developers: Use Tsetlin Machines with latency-aware training to speed up on-device classification tasks while maintaining accuracy.
Authors
Yefan Zeng, Shengyu Duan, Rishad Shafik, Alex Yakovlev
Abstract
The Tsetlin Machine (TM) is a logic-based machine learning model well suited to low-latency inference on resource-constrained edge devices. Because each clause is an AND over Boolean literals, both the literals and their associated Tsetlin Automaton (TA) actions can be represented at the bit level, enabling bitwise evaluation and an early exit that is triggered as soon as any included literal evaluates to zero, forcing the clause output to zero. In this work, we study how the two TM training hyperparameters, T and s, govern both classification accuracy and inference latency. Building on the inversely proportional T-s relationship along which accuracy is nearly constant, we find that inference latency is reduced primarily by increasing s; rather than exhaustively searching the (T, s) grid at high training cost, we propose a directed search strategy that treats accuracy as a constraint and advances toward larger s to reduce inference latency within a fixed evaluation budget. Experimental results on the gem5 simulator with an ARM processor show that, for certain datasets, the search is able to increase s while preserving the baseline accuracy, thereby reducing inference latency at negligible accuracy cost: across six datasets, the method reduces inference latency by up to 16.34%, while some datasets exhibit an accuracy reduction of only 0.06%. The proposed strategy requires far fewer configuration evaluations than an exhaustive grid search.