SoC floorplanning improved with faster, more accurate constraint handling
Toward Near-Optimal Floorplanning with Complex Design Constraints for Modern SoCs
Hardware Architecture
Summary
Designing computer chips is complicated because many rules must be followed at once, and ignoring them leads to bad results. The authors present a new step-by-step method that more strictly enforces these rules while making chip layouts. Their approach starts with a smart initial guess, then adjusts the design carefully to meet all constraints, and finally fine-tunes the layout to save space. Tests show their method runs faster and produces layouts closer to the best possible, with less wiring and smaller area than previous techniques.
What this means in practice
- •For chip design engineers: Create SoC layouts that strictly satisfy complex rules while reducing wirelength and area for better chip performance.
- •For integrated circuit layout teams: Deploy faster floorplanning algorithms that produce near-optimal designs respecting coupled constraints to accelerate development cycles.
Authors
Fuxing Huang, Hao Ai, Qiyuan Chen, Hao Wu, Wenxing Zhu, Xinning Liu, Ziran Zhu
Abstract
Modern system-on-chip (SoC) floorplanning is increasingly challenged by highly coupled complex design constraints. Existing methods often relax constraints into objectives via multi-objective optimization, leading to infeasible solutions or degraded quality. To address this, we formulate the problem as a constrained optimization task and propose a novel three-stage analytical framework integrating semidefinite programming (SDP), augmented Lagrangian method (ALM), and second-order cone programming (SOCP), which enforces constraints more rigorously and achieves higher-quality solutions. First, we adopt a two-step SDP formulation to obtain a robust initialization in the non-convex search space. Next, we incorporate differentiable objectives and constraints into an incremental ALM to jointly handle coupled design constraints during global floorplanning. Finally, an SOCP-based legalization strictly enforces feasibility while further reducing area. Experiments on the FloorSet benchmark show that our method satisfies all constraints with the fastest runtime. Compared with state-of-the-art methods, it reduces wirelength and area by 90\% and 16\% on average, and achieves near-optimal results, with wirelength and area being merely 2\% and 1\% larger than the ground-truth references, respectively.