Deep neural networks improve energy efficiency through voltage scaling adaptation
Adapting DNNs to Embrace Voltage Scaling Induced Errors via Accumulation-Aware Quantization
Hardware ArchitectureArtificial Intelligence
Summary
Lowering the voltage in computer chips saves energy but can cause errors that slow down processing. The authors found a way to train deep neural networks to avoid these errors by understanding how numbers add up inside the chip. Their technique tweaks the model so it avoids risky operations that cause mistakes at low voltages. This method helps save energy while keeping the accuracy of the neural network high.
What this means in practice
- •For hardware designers: Design energy-efficient neural network accelerators that maintain accuracy at low voltage by using accumulation-aware quantization and frequency scaling.
- •For embedded system developers: Implement low-power deep learning inference on advanced chips by integrating model training methods that adapt to hardware-induced errors at reduced voltages.
Authors
Alexis Maras, Panagiotis Chaidos, Georgios Alexandris, Dimitrios Soudris, Sotirios Xydis
Abstract
The pervasive deployment of Deep Neural Networks (DNNs) across the computing spectrum has brought growing attention to energy efficiency, alongside raw performance. While voltage scaling is a potent knob for power reduction, its application in next-generation nodes is hampered by severe throughput degradation and susceptibility to process variation. This work aims to address these energy-reliability trade-offs by introducing a hardware-software co-design methodology, based on the observation that timing-robust bit ranges within the accumulator of a systolic array vary significantly across different voltage-frequency operating points. At the software level, we propose an Accumulation-Aware Training approach that incorporates this information as a first-order optimization constraint during training. By integrating mixed-precision quantization with unstructured pruning, we effectively constrain the model's weight distribution to avoid activating the hardware's sensitized high-rank carry chains. At the architectural level, we complement this with selective MSB-masking and fine-grained clock-gating to minimize unnecessary dynamic switching activity. Furthermore, we employ a layer-wise Dynamic Frequency Scaling strategy to further adapt to the accumulator's reduced dynamic range, based on the numerical sensitivity of each layer. We experimentally evaluate the proposed solution on a deep scaled 2nm technology node and demonstrate that, when operating at a low-voltage frontier, our co-optimized post-layout architecture delivers substantial energy and energy-delay product gains of 39% and 23% respectively, relative to the nominal voltage implementation, while maintaining accuracy degradation within 1%.