Parallel processing cuts inner product latency and boosts energy efficiency
PARIS: Parallel Arithmetic Reduction and Integrated Selection for MSDF Inner Products
Hardware Architecture
Summary
Calculating inner products, a basic operation in neural networks, usually takes longer as more inputs are added because of serial processing. The authors developed a new hardware design called PARIS that processes many bits in parallel, speeding up these calculations without losing accuracy. Their design runs much faster and uses far less energy compared to previous methods when tested on digit recognition tasks. This approach can scale to larger systems and further reduce processing time by detecting certain patterns early.
What this means in practice
- •For hardware accelerator designers: Design specialized chips that speed up inner product calculations for neural networks with improved energy efficiency.
- •For embedded system developers: Integrate PARIS to enable faster and more energy-efficient neural network computations in resource-constrained devices.
Authors
Malik Zohaib Nisar, Ic-Pyo Hong, Dorit Merhof, Muhammad Usman
Abstract
Existing most-significant-digit-first (MSDF) accelerators serialize input-term processing, causing inner-product latency to increase with fan-in. This paper presents PARIS, an MSDF architecture that eliminates input-term serialization through parallel bit-plane reduction and shared carry-save residual selection. For $B$-bit operands, PARIS processes $B^2$ bit-position pairs, independent of fan-in within the supported tile, while generating exact MSDF outputs. Synthesized in 45\,nm at 100\,MHz, the 784-lane INT8 core occupies 0.008701\,mm$^2$ and completes an inner product in 88 cycles. Evaluation on two MNIST multilayer perceptrons demonstrates arithmetic-workload speedups of 240.44$\times$ and 180.47$\times$ over a matched reused-MSDF implementation, reducing arithmetic energy by 98.89\% and 98.58\%, respectively. A synthesized 16-engine accelerator occupies 0.90273\,mm$^2$ and meets the 100\,MHz timing constraint. Assuming immediate weight availability, it delivers a projected throughput of 24.33\,GOPS and an estimated energy efficiency of 1,581.14\,GOPS/W at unchanged mapped power. Bias-aware ReLU detection further reduces modeled arithmetic cycles by 5.52\% and 4.86\%. A separate 256-engine RTL implementation completes Model A in 259 cycles, demonstrating output-parallel scalability.