Continuous probabilistic computer greatly speeds up solving and memory tasks
First hardware demonstration of a continuous-state probabilistic computer with programmable energy-defined sampling
Neural and Evolutionary ComputingEmerging Technologies
Summary
Probabilistic computers help solve tricky problems by exploring many options quickly. The authors present a new kind of probabilistic computer that uses continuous variables instead of just on/off bits, making it better at certain tasks. They built a prototype on an FPGA that runs much faster at factoring numbers and recalling images compared to standard software. This new design could let future devices solve complex problems more quickly and efficiently.
What this means in practice
- •For hardware engineers: Create fast custom processors that use continuous probabilistic bits to solve optimization and memory tasks more efficiently.
- •For machine learning developers: Use hardware-accelerated continuous probabilistic computing to speed up exploration of solution spaces for training and inference.
Authors
Chao Fang, Hsuan Yao Tu, Yihan He, Xiao Gong, Chin-Fu Nien, Gengchiau Liang
Abstract
Probabilistic computing has proved useful for combinatorial optimization, but conventional implementations rely on binary stochastic units and sigmoid-based updates. Extending these systems to continuous variables requires binary encoding. Here we introduce a continuous probabilistic computer (CPC) whose continuous probabilistic bits sample bounded states from conditional distributions defined by local energies. Separating random-source generation from conditional sampling provides a route to using physical random sources with different native distributions. A field-programmable gate array (FPGA) prototype updates finite-precision states using digital randomness. The same framework supports product constraints, memory recovery and solution-space exploration. For the tested 7-bit factorization case, fixed-temperature FPGA CPC reduces mean core solving time approximately 33,000-fold relative to the evaluated quadratic unconstrained binary optimization software implementation. The FPGA recovers stored MNIST patterns without pretrained networks, achieving final success rates of 100%. Software CPC reaches 90% reference coverage of the feasible area in approximately 18% of the time required by restarted Adam.