Quantum error correction decoding accelerated on NVIDIA GPUs with mixed precision
Engineering Low-Latency, High-Throughput Quantum Decoders on NVIDIA GPUs
Distributed, Parallel, and Cluster Computing
Summary
Quantum computers are very sensitive to errors, so fixing these errors quickly is important. The authors created a fast program that runs on NVIDIA graphics cards to identify and correct these errors using smart steps to speed up the process. They used special tricks like mixed precision math and batching tasks so the program runs faster without losing accuracy. Their method works well on different types of quantum error correction codes and hardware, including consumer-grade GPUs. This work helps make building reliable quantum computers more practical using existing hardware.
What this means in practice
- •For quantum computing hardware teams: Deploy fast quantum error correction decoders on commodity GPUs to reduce latency and improve throughput in quantum devices.
- •For high performance computing engineers: Implement throughput-optimized error correction algorithms using mixed precision and quantized arithmetic on NVIDIA GPUs for efficient decoding tasks.
Authors
Stefano Markidis, Luca Pennati, Ivy Peng
Abstract
We design and optimize a quantum error correction (QEC) decoder for NVIDIA GPUs, combining Relay belief propagation, a state-of-the-art message-passing algorithm, with order-zero ordered statistics post-processing. Our implementation uses CUDA Graphs to control GPU execution, stops updates for converged samples, and collects unresolved samples in queues for post-processing. We optimize sparse traversal through coalesced message accesses, prefetching, and register reuse, and accelerate binary post-processing with warp-level collectives. In addition, mixed FP16-FP32 arithmetic and INT8 quantization reduce message storage and traffic while retaining accuracy using accumulators at higher precision. We evaluate surface, hypergraph product, and bivariate bicycle code workloads on NVIDIA A100 and GH200 data-center GPUs and a commodity RTX 5080. On the bivariate bicycle code at error probability 0.003, INT8 halves amortized decoding time relative to independently tuned FP32 with a negligible logical error rate increase on RTX 5080. With independent syndrome batches submitted back-to-back to concurrent decoder instances, RTX 5080 delivers 91% of GH200's highest measured throughput with an 8.9x shorter median submission-to-correction latency. The combination of performance optimization, mixed precision, INT8 quantization, and concurrent decoder instances opens a path toward QEC decoder clusters built from commodity GPUs.