Floorplanning improves chip design by optimizing polygonal module shapes
RPolyPlan: A Unified Global Floorplanning and Legalization Framework for Rectilinear Soft Modules
Hardware Architecture
Summary
Placing parts on a computer chip efficiently is tricky because the parts can be different shapes and sizes. This paper introduces a method to directly change the shapes of chip parts into flexible polygon forms during the whole design process, not just after an initial step. By doing this, the parts fit better together, reducing wasted space and the length of internal wiring. The authors also created a way to fix any overlaps and keep the parts properly arranged while meeting all design rules. Their approach showed better results on well-known benchmarks compared to earlier methods.
What this means in practice
- •For chip design engineers: improve chip layouts by optimizing flexible module shapes for better area use and shorter wiring
- •For embedded systems developers: reduce chip size and signal delay by using advanced floorplanning that adapts module shapes dynamically
Authors
Fuxing Huang, Wenxing Zhu, Xinning Liu, Ziran Zhu
Abstract
Floorplanning with rectilinear soft modules improves area utilization and wirelength by allowing modules to adapt to rectilinear polygon (RPoly) shapes. Existing methods typically construct rectilinear polygons through incremental refinement after obtaining a rectangular global solution, which confines polygon exploration to the neighborhood induced by the initial floorplan. This paper presents RPolyPlan, a unified framework for outline-free and fixed-outline floorplanning that directly incorporates continuously deformable rectilinear polygons into global floorplanning. To enable direct polygon optimization, we introduce a structured continuous representation and a differentiable polygon shaping model that dynamically optimizes rectilinear module shapes based on overlaps, making continuous shape optimization feasible for gradient-based global floorplanning. An augmented Lagrangian formulation robustly handles the coupled inequality constraints, provides theoretical convergence guarantees, and reduces dependence on manual penalty-parameter tuning. During legalization, minimum-cost flow and rectangular decomposition determine the target areas of subrectangles, and horizontal and vertical constraint graphs encode their geometric relations. The resulting convex legalization formulation satisfies the area, shape, separation, connectivity, and outline constraints while minimizing either the chip area or the displacement from the global floorplanning solution. Experiments on the GSRC, MCNC, and ICCAD 2023 contest benchmarks demonstrate that RPolyPlan reduces HPWL over the evaluated state-of-the-art methods by 7% and 6% in fixed-outline and outline-free experiments, respectively.