Fpga speeds up client-side homomorphic encryption encoding and encryption
A Combined Streaming FPGA Architecture for Client-Side CKKS Encoding and Encryption
Cryptography and SecurityHardware Architecture
Summary
Homomorphic encryption lets you perform calculations on data while keeping it secret, but preparing the data first takes time. The authors created a special FPGA design that shares hardware efficiently to speed up this preparation step called CKKS encoding and encryption. Their design processes parts both sequentially and in parallel on the chip, avoiding slow memory use. This makes encrypting millions of data points faster than typical CPU software solutions.
What this means in practice
- •For security hardware designers: Build specialized FPGA accelerators to encrypt client data for privacy-preserving cloud computing with higher throughput than CPUs.
- •For embedded system developers: Develop efficient embedded devices that prepare encrypted data faster for secure edge computing environments.
Authors
Joseph Kurina, Bogdan Pasca, Suleyman Demirsoy, Sunwoong Kim
Abstract
Homomorphic encryption allows a computing service to process encrypted data, but the client must first encode and encrypt its inputs. Sharing hardware between floating-point encoding and modular encryption reduces area but requires those transform roles to execute at different times. We present a streaming FPGA architecture for CKKS encoding and encryption that computes the shared floating-point encoding transform once and performs the integer transforms for six residue moduli in parallel. Dedicated transform pipelines exchange intermediate results on chip rather than through off-chip memory. DSP Builder generates the transform RTL, and Altera HLS IP Gen compiler compiles the surrounding SYCL pipeline into IP integrated with DMA and control logic in an accelerator functional unit. At polynomial degree N = 8192, the Altera Agilex 7 implementation delivers 5,143 complete ciphertexts per second at 471 MHz. One SEAL-Embedded CPU worker on the same workstation delivers 113 ciphertexts per second for real-valued inputs using all 4,096 slots. Measurements cover prepared-input computation through complete ciphertext construction, including FPGA submission and output delivery.