E-Layout improves chip timing and area by reshaping circuit logic
E-Layout: Layout-Stage Logic Restructuring via RL-Optimized Equality-Saturated Graph Retrieval-Augmented Generation
Hardware Architecture
Summary
Making computer chips run better and faster depends a lot on how their tiny parts are arranged and connected. The authors created E-Layout, a smart method that reshapes the way chip circuits are organized after their parts are placed, using a mix of logic changes and physical adjustments. It tries out many equivalent ways to redesign the circuits and uses machine learning to pick the best combos for timing and size. Testing on several chip designs, E-Layout showed improvements in speed and reduced the chip area slightly compared to top industry methods.
What this means in practice
- •For ic physical design teams: Optimize chip designs by restructuring logic after placement to improve timing and reduce area using E-Layout’s combined logic and physical optimization approach.
- •For hardware verification engineers: Use logic equivalence-preserving alternatives generated by E-Layout to better analyze timing-critical chip sections under real layout conditions.
Authors
Wenji Fang, Rongjian Liang, Yi-Chen Lu, Cunxi Yu, Chen Chen, Shang Liu, Chenhui Deng, Wenkai Li, Haoxing Ren, Zhiyao Xie
Abstract
Achieving high sign-off performance in advanced ICs increasingly depends on layout-stage optimization under realistic physical conditions. While recent efforts have moved toward synthesis-layout fusion, most existing works still focus on bringing estimated physical information earlier into synthesis, whose optimization does not fully correlate with real layout-stage behavior. Meanwhile, layout-stage optimization remains largely restricted to a fixed logic structure, relying mainly on buffering and sizing. This fundamentally constrains the optimization space under realistic physical conditions. To address this, we present E-Layout, an ML-driven framework for post-placement layout restructuring. E-Layout jointly optimizes logic transformation and physical implementation across multiple subcircuits under design-level timing feedback. This enables the selection of the most timing-beneficial set of disjoint restructured subcircuits to form the optimized circuit. Specifically, it first constructs equivalence-preserving logic alternatives via e-graph equality saturation, then couples logic selection with physical realization through a graph-based retrieval-augmented generation (RAG) model, and finally refines these local logic-physical decisions with reinforcement learning under design-level timing feedback. Evaluated on 9 diverse designs, it achieves on average 6% TNS improvement and 2% WNS improvement, while even reducing area by 1%, over an industry-leading commercial physical design flow.