Cryogenic testing improves 22 nm chip designs for quantum control
Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
Hardware Architecture
Summary
Controlling quantum computers is hard because their parts work best near absolute zero, but the control electronics usually sit at room temperature, causing delays. The authors studied a common chip design used in modern electronics and tested how it behaves when cooled to cryogenic temperatures. They found that changing the voltage applied to certain parts of the chip can greatly improve speed and power efficiency at these cold temperatures. This work helps designers use existing chip libraries in very cold environments without redesigning them from scratch.
What this means in practice
- •For semiconductor chip designers: Incorporate cryogenic recharacterization into design flows to optimize digital control circuits for operation near 4 K without changing layouts or cell functions.
- •For quantum computing hardware teams: Use improved characterization of standard-cell libraries at cryogenic temperatures to place digital control electronics closer to quantum processors, reducing wiring delays.
Authors
Mohamed Gharib, Rami Rasheedi, Salma Abdelzaher, Henry Shi, Mike Hammer, Llorenç Fanals-i-Batllori, Aldo Pena Perez, Antonino Miceli, Inna Partin-Vaisband
Abstract
Wiring and bandwidth bottlenecks between a quantum processor and room-temperature electronics can be reduced by placing digital control at the cryogenic stage, but commercial foundry standard-cell libraries are not specified for operation at 4 K. A cryogenic recharacterization flow is therefore developed for a commercial 22 nm FD-SOI foundry standard-cell library using commercially available cryogenic compact-device models, while retaining the original cell circuits, layouts, logic functions, and implementation semantics and remaining compatible with the commercial synthesis, place-and-route, and signoff methodology used at room temperature. Body-bias dependence is quantified over 38,640 matched slew/load points at zero, +/-0.9 V, and +/-1.8 V body bias. Relative to full bias, zero-bias operation increases the median rising and falling delays by 38.6x and 33.0x, while approximately 90% of transitions exceed the foundry-defined maximum-transition envelope. The 0.8 V-to-0.4 V level shifter is even more sensitive to body bias: its worst-case falling delay decreases from 30.6 ns at zero bias to 0.56 ns at +/-1.8 V. For the outbound 0.4 V-to-0.8 V crossing, driving the 0.8 V receiver without a level shifter dissipates 57.7 uW of static power per bit at full bias, against 0.196 nW when level-shifted. In post-route analysis of the unchanged extracted physical database of a fabricated 32-bit ALU, the register-to-register setup boundary increases from 1.3 MHz at zero bias to 37.9 MHz at +/-0.9 V and 132.9 MHz at +/-1.8 V.