Summary
Small processors built using the RISC-V instruction set usually take up more space and run slower than they could on FPGA chips. The authors built a very small and fast RISC-V processor that runs at over 700 MHz and can handle one instruction per clock cycle when conditions are perfect. They also created a way to customize the processor to only include the parts an application really needs, making it even smaller and faster. Although these special processors still understand the original program’s assembly instructions, they aren’t compatible with all RISC-V binary files anymore. The authors tested their designs on different RISC-V configurations and showed that many of these processors could fit into an FPGA predictably without slowing down.
What this means in practice
- •For fpga hardware engineers: Design and deploy custom lightweight RISC-V CPU cores that run fast and use less chip space for embedded FPGA systems.
- •For embedded system developers: Integrate optimized, application-specific RISC-V processors into FPGA-based products to improve performance and minimize resource usage.
Abstract
RISC-V processors are now widely available for FPGAs, with most FPGA vendors replacing their proprietary soft-CPU architectures with this instruction-set architecture (ISA). Although contemporary FPGAs are increasingly resource- and feature-rich, a soft processor system---including memory---often occupies a disproportionately large footprint and delivers only modest performance relative to the potential of the target device. In this work we first design a lightweight but deeply pipelined RISC-V core that can run above 700 MHz in a mid-range device and that is capable of retiring one instruction per clock under ideal conditions. We then develop and demonstrate a new optimization method that compiles the final application binary and a specialized processor instance contemporaneously. The method expands each instruction into an application-specific encoding, removes unused datapath and decode logic during synthesis, and yields cores that remain assembler-compatible with the original program while no longer being binary-compatible with a general-purpose RISC-V. We implement example designs on RV32I (base integer), RV32M (integer multiply), and RV32F (single-precision floating-point) configurations. Our optimized RISC-V is as small as 170 ALMs and closes timing at 775 MHz in an Altera Agilex-5 device. Finally, we show that these processors can be packed into a deterministic area and stepped-and-repeated continuously without material impact on performance, enabling predictable multi-core density planning.