Causal analysis reveals hidden CPU performance bottlenecks
Top-Down Microarchitecture Analysis Without Causal Modelling Is Dangerous!
Performance
Summary
Common methods for finding slowdowns in computer processors focus on only one cause of delay, missing other important factors. The authors show that ignoring these hidden causes can lead to wrong conclusions and wasted efforts in improving hardware. They introduce a new analysis approach called CTMA that maps out all key causes affecting performance. Testing on various CPUs, they uncover surprising effects like how reducing certain CPU activities can actually help some workloads run faster. Their method also finds unusual behavior in Intel processors that artificially inflates performance numbers.
What this means in practice
- •For hardware architects: Identify real CPU performance bottlenecks by analyzing all key causes rather than relying on traditional single-path methods.
- •For compiler engineers: Optimize software by detecting how algorithms impact instruction counts and CPU efficiency, avoiding misleading hardware assumptions.
Authors
Chenxi Wang, Lei Wang, Wanling Gao, Guoxin Kang, Fanda Fan, Jianfeng Zhan
Abstract
Top-Down Microarchitecture Analysis (TMA) is the standard for identifying CPU bottlenecks. However, TMA implicitly models performance via a single causal path: Workload(dataset, algorithm) => CPU(CPI) => System(Performance) (microarchitectural efficiency path). It overlooks two hidden causal paths: Workload(dataset, algorithm) => Instructions(Retired) => System(Performance) (algorithmic efficiency path) and Workload(dataset, algorithm) => Instructions(Retired) => CPU(CPI) => System(Performance) (microarchitecture-algorithm efficiency path). This causal blindness often misleads architects into futile hardware optimizations. To address this, we propose Causal Top-Down Microarchitecture Analysis (CTMA). Utilizing the object causal model, CTMA explicitly models these three causal paths among the workload, instructions, CPU, and system. We validate CTMA across Intel, AMD, and ARM platforms. Our experiments reveal counterintuitive insights: (1) CPI Profiling Blindness: Algorithmic instruction bloat can double elapsed time while the CPI profile remains frozen. (2) Over-Speculation Congestion: Throttling the Frontend paradoxically improves performance in pointer-chasing algorithms. (3) ILP Window Collapse: Extreme data topologies shift bottlenecks from Backend ROB capacity to Frontend fill-rate starvation. (4) Op-Cache SMT Overlap: Ultra-small footprints yield SMT speedups on Intel but cause severe thrashing on AMD. (5) "Ghost State" Artifact: Stale pipeline mitigations on Intel Xeon Gold 5120T artificially boost performance by 22.75% on SPEC CPU2017 and 42.2% on SPEC CPU2026. Based on this, we propose a dynamic speculation throttling mechanism.