Efficient hardware design improves sparse spiking neural networks
PSA: A Pruning-Friendly Sparse-Aware Accelerator for Efficient Sparse Convolution in SNNs
Hardware Architecture
Summary
Spiking neural networks are brain-inspired models that use less energy by processing only important spikes. But when parts of these networks are removed or 'pruned,' the computations become irregular and hard for hardware to handle efficiently. The authors introduce PSA, a new hardware design that makes these irregular sparse computations much faster and more energy-efficient. They tested PSA on common datasets and found it uses much less energy and is much faster than traditional dense methods.
What this means in practice
- •For neural network hardware developers: Design hardware accelerators that efficiently run pruned spiking neural networks with irregular sparse activations.
- •For embedded systems engineers: Deploy energy-efficient spiking neural networks in low-power devices by integrating PSA-friendly pruning and sparse convolution methods.
Authors
Sanhe Fu, Kainan Wang, Bo Wang, Aili Wang
Abstract
Spiking neural networks (SNNs) are promising for energy-efficient artificial intelligence due to their event-driven sparse computation, and neuron pruning can further reduce redundant operations. However, in practical hardware accelerators, spike sparsity and pruning-induced sparsity produce highly irregular sparse workloads that are difficult to execute efficiently. Existing approaches do not jointly support sparse-input execution, low-overhead sparse convolution lowering and pruning-friendly execution. This paper presents PSA, a Pruning-friendly Sparse-aware Accelerator for efficient sparse convolution in SNNs. PSA features a Sparse-Aware Merge-Accumulation (SAMA) dataflow that aligns sparse spike indices and converts irregular activations into continuous computation streams for efficient sparse convolution execution. It further introduces a Sparse Implicit Group-wise im2col (SIG-im2col) convolution lowering mechanism that converts sparse convolution into SpMM on-chip with low mapping cost and memory overhead. In addition, PSA integrates a lightweight pruning-friendly gating mechanism to directly support pruned SNNs. Results on ResNet-18/CIFAR-10 show that PSA achieves a 4.45x improvement in energy efficiency and an 18.52x reduction in energy-delay product (EDP) over the dense baseline.