Helix FPGA accelerator speeds up diverse Krylov solvers with low overhead
Helix: A Unified Programmable Accelerator for Diverse Krylov Subspace Solvers
Hardware ArchitectureDistributed, Parallel, and Cluster Computing
Summary
Solving large sparse linear equations is important but computationally challenging, and specialized hardware often only handles a single solution method. This paper presents Helix, a new FPGA accelerator that can run many types of algorithms for these problems without changing hardware. The authors designed Helix to work with common building blocks shared by different algorithms and use programmable parts to switch quickly between methods. Helix matches or beats existing tools in speed and energy use, while adding almost no delay or resource cost for its programmability.
What this means in practice
- •For high performance computing teams: Accelerate a broad set of sparse linear system solvers on a single FPGA platform with minimal switching overhead.
- •For data center hardware engineers: Implement energy-efficient, programmable sparse solver accelerators that can adapt to various solver algorithms without hardware redesign.
Authors
Wei Chen, Yizhi Yuan, Linghao Song
Abstract
Domain-specific accelerators deliver high performance and energy efficiency through specialization but often lack support for extensible algorithm families. Existing FPGA accelerators for Krylov subspace methods, which iteratively solve sparse linear systems, typically support a single solver or require separate hardware configurations. Helix follows a systematic algorithm-family design methodology that first abstracts common computational primitives from diverse Krylov solvers and builds the architecture around efficient, programmable primitive kernels. Helix then introduces programmable datapaths to coordinate these primitives. Its architecture decouples hardware implementation from solver-specific execution, enabling HBM reuse and zero solver-switching latency. Finally, Helix provides a DSL compiler that efficiently maps different solvers onto the architecture while optimizing vector-operation performance for each solver. We prototype Helix on a Xilinx Alveo U55C FPGA and evaluate Helix's practicality and performance by using it to compile and execute eight solvers. Helix achieves up to 7.91x and 1.16x speedups over Xilinx XcgSolver and the state-of-the-art FPGA accelerator Callipepla, respectively, both of which support only JPCG. Across the eight solvers, Helix sustains 47.5% - 96.9% of the throughput of an NVIDIA RTX PRO 6000 GPU while delivering 2.29x - 4.66x higher energy efficiency and 1.89x - 3.85x higher throughput per unit peak memory bandwidth. The programmable components incur 0.25% - 0.57% execution-time overhead and 4.7% LUT and 4.0% FF overhead, demonstrating negligible overhead for programmability.