Low-latency adders designed using printed memristors speed up computing
Cross-Layer Co-Design of Low-Latency Stateful Logic Adders with Printed Memristors
Emerging Technologies
Summary
Moving data between memory and processors slows down computers. The authors worked on a way to do math directly where data is stored using special devices called memristors. They created a method combining different logic steps and hardware designs to make adding numbers faster. Their design uses fewer steps than older methods, making addition tasks run much quicker. This shows that designing devices and computing methods together can lead to better performance.
What this means in practice
- •For hardware engineers: Build faster, low-power adders using printed memristors for embedded and edge computing devices.
- •For circuit designers: Design arithmetic circuits that minimize cycle counts by using co-designed logic sequences and datapath architectures with memristive devices.
Authors
Fabian Seiler, Kerem Kagan Güclü, Hongrong Hu, Gabriel Cadilha Marques, Jasmin Aghassi-Hagmann, Nima TaheriNejad
Abstract
Data movement between memory and processing units remains a major bottleneck in data-centric systems. Memristive Stateful Logic (SL) addresses this problem by performing Boolean operations directly on stored resistive states. However, arithmetic efficiency depends jointly on the device-supported logic primitive set, the dependency structure of the resulting operation sequence, and its mapping to datapath architectures. While prior designs typically optimize device, logic, and architecture layers separately, we jointly consider them to co-design a stateful adder. We experimentally demonstrate a mixed MAGIC and FELIX logic primitive set on printed Electrochemical Metallization (ECM) memristors and derive a full adder sequence optimized for inter-bit carry propagation. Mapping this sequence to bit-serial, bit-parallel, and bit-pipelined datapaths reduces the latter two to 2n+6 cycles for an n-bit addition. For 32-bit addition, this requires 60-88% fewer cycles than prior SL adders. Across four representative workloads, we achieve 3.7x-16.4x speedup over prior. These results show how cross-layer co-design can translate into improved workload-level performance.