LLM-guided framework improves post-route FPGA timing closure
LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation
Artificial Intelligence
Summary
Making field-programmable gate arrays (FPGAs) run faster after design is tricky and usually needs expert help. The authors created LATCH, a two-part system that uses large language models (LLMs) to guide timing improvements while relying on reliable, rule-based FPGA tools for implementation. They found a balance between how much control the AI has and how reliable or effective the timing fixes are. Using multiple rounds and smart exploration methods improved the speed of many designs. One key technique that helped was moving hard blocks in the designs.
What this means in practice
- •For fpga design teams: Optimize FPGA timing closure after routing by integrating LLM-driven recipe orchestration to enhance design frequency performance.
- •For hardware accelerator developers: Improve post-route frequency of custom hardware on FPGAs using multi-iteration LLM-based exploration guided by expert heuristics.
Authors
Shu Gu, Matthew Youngman, Yuqin Zhao, Cristian Sestito, Ali Siddique, Ramesh Krishnamurthy, Danial Chitnis, Themis Prodromakis
Abstract
Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates large language model (LLM) orchestration from deterministic FPGA implementation and evaluation. Across sixteen designs and seven LLMs, a single-iteration study compares three agent control granularities - expert-written recipes, direct EDA operations and LLM-constructed procedures - to ask how much control an agent needs per attempt. Functional-pass rates are 98.2%, 71.4% and 17.9%, respectively; yet direct operations give slightly larger 3.4% median Fmax gains when passing, versus 3.2% for recipes. This exposes a trade-off between execution reliability and timing improvement. Informed by this trade-off, a multi-iteration study fixes the action tier at expert recipes to ask how repeated attempts are best organised, comparing a fitted deterministic heuristic with sequential LLM reasoning, branching exploration and knowledge base-guided exploration within 12 checkpoints per run. Branching raises mean maximum-frequency improvement from 10.5% (sequential) to 16.0%, and the knowledge base to 20.3%, improving 15 of 16 designs. Characterisation across 2,421 recipe attempts profiled their gain and validation rates, showing hard-block re-placement gives the largest cumulative mean gain at 41.4MHz.