Chiplet design space exploration improved with AI guided optimization
LLM-Augmented Bayesian Optimization with Adaptive Policies for Chiplet Design Space Exploration
Machine Learning
Summary
Designing advanced chiplets that combine CPUs and GPUs is tricky because testing many options is slow and complicated. The authors created a new approach that uses an AI language model to guide a smart search method called Bayesian Optimization, making it easier and faster to find good chip designs. They improved a chip simulation tool to work with 3D designs and developed ways for the AI to give better guidance during the search. Their experiments show this approach helps explore chip designs more efficiently.
What this means in practice
- •For chip architects: Automate and speed up the design exploration of CPU-GPU chiplets with AI-guided optimization policies.
- •For semiconductor simulation teams: Enhance chiplet simulation tools to support 3D design topologies for better evaluation of complex heterogeneous systems.
Authors
Hang Liu, Zhengfei Chen, Zhengrui Chen, Hao Geng, Yu Li, Qi Sun
Abstract
Chiplet technology is a key approach for extending Moore's Law. However, its design process is constrained by two primary challenges: the scarcity of early-stage platforms for rapidly evaluating chiplet-based heterogeneous systems, and the complex relationships between design parameters and optimization metrics. To address these challenges, we propose a synergistic framework that integrates a Large Language Model (LLM) with Bayesian Optimization (BO), enabling architectural-level simulation and automated optimization for the 2.5D/3D CPU-GPU heterogeneous chiplets. We extend the open-source chiplet simulator to evaluate 3D designs by supporting graph topologies. Further, to enhance the exploration efficiency of BO, we introduce an LLM that generates high-quality policies to guide the optimization process, enabled by our proposed adaptive directional policy reasoning (ADPR) and an exploration gain-aware fine-tuning method. Finally, we use the policy-guided BO to perform an automated and efficient exploration of the complex chiplet design space. Experiments on 2.5D and 3D chiplet reveal that our framework improves design space exploration efficiency.