TPCS speeds up cycle-level RTL simulation with accurate design generation
TPCS: A Cycle-Level Simulation Paradigm with Native Execution Semantics for RTL Modeling and Generation
Hardware Architecture
Summary
Designers need fast and precise computer models to test new microchips before building them. The authors introduce TPCS, a new method that simulates chip designs cycle by cycle much faster than existing tools, while keeping results very accurate. It does this by only running important parts of the design each cycle and making it easy to turn these models into real hardware. Their tests showed significant speed improvements without losing detail, helping chip creators explore designs more quickly.
What this means in practice
- •For hardware design teams: Run cycle-accurate simulations faster during microarchitecture exploration without losing fidelity, enabling quick early-stage hardware evaluation.
- •For hardware accelerator developers: Generate synthesizable RTL from high-level models efficiently to help debug and optimize accelerator designs while preserving performance.
Authors
Chengzhen Meng, Xiaoyu Li, Chen Bai, Zhenyu Zhang, Hongjun Dai
Abstract
The growing diversity of domain-specific architectures and microarchitectural designs demands fast and accurate evaluation methods during early design stages. However, existing approaches suffer from a fundamental trade-off: high-level simulators offer speed but lack fidelity, while RTL-based tools provide accuracy at the cost of significant simulation overhead. This gap limits efficient pre-RTL microarchitecture exploration. Therefore, we propose Transaction-Pruned Cycle Simulation (TPCS), a novel modeling and simulation framework. It serves as a unified intermediate abstraction spanning microarchitecture modeling, cycle-accurate simulation, and synthesizable RTL implementation. TPCS organizes combinational logic as transaction-based function invocations and leverages host CPU control flow to naturally prune inactive logic, eliminating the need for explicit event scheduling or signal tracking. This enables cycle-accurate simulation with significantly improved performance. TPCS preserves structural correspondence with RTL and supports automatic generation of synthesizable designs. TPCS achieves 36$\times$-42$\times$ speedups over parallel Verilator on SMP systems and 3.4$\times$-7.2$\times$ over single-threaded Verilator on accelerators, with cycle-level waveform agreement on the evaluated traces. The generated RTL demonstrates comparable timing and area to handcrafted implementations, with relative changes of -4.7\% to +2.6\% in clock period and -3.3\% to +4.0\% in standard-cell area. By bridging the abstraction gap between high-level modeling and RTL design, TPCS enables a unified and agile pre-RTL workflow, allowing efficient microarchitecture exploration with both high performance and implementation fidelity.