Automated construction of detailed hardware knowledge graphs from datasheets
Faithful and Complete LLM-Assisted Automated Construction of Hierarchical Hardware Knowledge Graphs
Artificial Intelligence
Summary
Hardware datasheets are long and complex, making it hard for engineers to find all the important details needed to build and check hardware systems. The authors created a step-by-step method that uses large language models to carefully read, organize, and verify information from these datasheets into clear and reliable knowledge graphs. These graphs keep track of the original sources and help ensure no key facts are missed. Tests show this method finds almost all correct details, doing much better than simpler ways. This helps engineers make safer and more accurate hardware design choices.
What this means in practice
- •For hardware design engineers: Access structured, source-traced hardware specifications to improve component selection and system integration accuracy.
- •For verification engineers: Use comprehensive knowledge graphs to detect overlooked constraints and reduce errors in hardware compatibility checks.
Authors
Haotian Qiao, Robert P. Dick
Abstract
Hardware datasheets contain engineering specifications essential for component selection, system integration, and hardware compatibility verification. However, manual inspection is tedious and error-prone because datasheets are lengthy and heterogeneous, with dense information fragmented across tables, figures, and text. Although large language models (LLMs) can automate this process, naïve one-shot processing omits relevant specifications even when the document fits within the model's context window. We present an automated LLM-driven pipeline that transforms hardware datasheets into general-purpose hierarchical hardware knowledge graphs through chunk-based property extraction, hierarchical routing, and iterative refinement. The framework uses LLMs for information extraction and semantic reasoning while preserving source provenance and applying graph updates through validated instructions and deterministic local execution. This staged design reduces per-query context and maintains traceable intermediate representations. The resulting knowledge graphs provide semantically organized, source-grounded hardware properties for downstream retrieval and reasoning. We evaluate the framework on 20 hardware datasheets spanning diverse component types and document lengths. We assess property faithfulness and introduce inter-graph completeness to measure relative semantic coverage without exhaustive ground truth. Our framework achieves 98.8% property faithfulness compared with 76.1% for the one-shot baseline, while fully covering 83.6% of faithful baseline properties; in the reverse direction, the baseline fully covers only 10.5% of ours. These improvements provide more reliable and comprehensive engineering information for downstream hardware design and verification, reducing the risk of overlooked constraints and incorrect decisions.