MSDF method cuts brain tumor scan energy consumption during AI processing
DEX: Digit-Level Early Exit for Energy-Efficient MSDF Neural Network Inference
Hardware ArchitectureArtificial IntelligenceMachine Learning
Summary
Processing brain tumor images with AI requires a lot of energy and computing work. The authors designed a special chip that looks at parts of the calculation step-by-step from the most important digits first, allowing it to stop early when confident, saving energy. Their chip uses this to reduce work by over a third with only a small drop in accuracy compared to full precision methods. This helps make brain tumor image analysis faster and more energy-efficient without changing the AI model's stored data.
What this means in practice
- •For medical imaging teams: Reduce computation energy when running brain tumor segmentation models on hardware accelerators without sacrificing accuracy.
- •For hardware accelerator designers: Incorporate digit-level early exit mechanisms in MSDF arithmetic units to lower energy consumption during neural network inference.
Authors
Yousef Sadegheih, Dorit Merhof, Muhammad Usman
Abstract
U-Net inference for brain-tumor segmentation requires billions of multiply-accumulate operations, motivating hardware that can reduce computation dynamically rather than relying only on fixed precision or static model compression. Most-significant-digit-first (MSDF) arithmetic exposes the leading digits of a result during computation, enabling output-dependent decisions before the full value is generated. This paper presents an MSDF accelerator for quantized U-Net segmentation with a two-stage grouped processing element supporting signed INT8 operands and in-stream bias accumulation. Four runtime mechanisms operate directly on the output digit stream: exact early negative detection (END) in ReLU layers, exact sign-only decision making in the segmentation head, calibrated low-order-digit skipping, and calibrated pruning. The two approximate mechanisms are selected offline under an accuracy constraint, while execution requires only lightweight control and does not modify the stored weights. On a residual U-Net trained with nnU-Net for BraTS, the proposed mechanisms reduce digit cycles by 38.38\% while achieving a mean Dice score of 80.58\% on 73 held-out cases, compared with 81.20\% for the floating-point model; the exact mechanisms alone reduce cycles by 18.79\% without altering the quantized output. Synthesized in 45~nm, the processing element operates at 500~MHz, occupies 0.858~mm$^2$, and consumes 0.726~mJ per $192\times192$ patch under switching-activity-annotated power analysis. A projected eight-output accelerator with shared activation delivery achieves 16.6~ms latency and 1.67~mJ per patch.